EPC1L20 vs EPC1LI20 Comparaison
Comparaison détaillée côte à côte de EPC1L20 par Altera et EPC1LI20 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC1L20 | EPC1LI20 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | Memory ICs | Memory ICs |
| Statut du cycle de vie | Actif | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $3,75 | $8,50 |
| Type de mémoire | OTP Configuration PROM (Flash) | OTP Configuration PROM (EPROM-based) |
| Taille de mémoire | 1 Mbit | 1 Mb (1,048,576 bits) |
| Configuration Clock (max) | 8 MHz | — |
| Flash Access Time | 90 ns (approx.) | — |
| Max Read Bandwidth | 160 Mbps (16-bit DQ bus) | — |
| Interface | Serial / FPP configuration + JTAG (IEEE 1149.1) | — |
| Tension d'alimentation | 3.3 V (typical) | — |
| Programmability | One-Time Programmable (OTP) | — |
| Boîtier | 20-pin PLCC (9x9 mm) | 20-pin PLCC (J-lead, 9x9 mm) |
| Type de montage | Through-Hole / Socket | Surface Mount (PLCC socket compatible) |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| JTAG / ISP Support | Yes (IEEE 1149.1) | — |
| Compatible FPGA Series | Stratix, Cyclone, APEX, FLEX, ACEX, LUT-based families | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status - original Altera part may be non-RoHS SnPb finish] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Configuration Interface | — | Altera Passive Serial / Altera Active Serial / JTAG (IEEE 1149.1) |
| Maximum Configuration Clock | — | 8 MHz |
| Supply Voltage (VCC) | — | 5.0 V (4.75 V to 5.25 V) |
| Programming Voltage (VPP) | — | 12.75 V (typical, factory-programmed via JTAG) |
| Nombre de broches | — | 20 |
| Cascading Support | — | Yes (nCASC pin for multi-device daisy chain) |
| Endurance | — | OTP (one-time programmable, 1000 erase-equivalent UV cycles for pre-program erase) |
| JTAG Programming | — | Yes (in-system via IEEE 1149.1) |
| Compatible FPGA Families | — | FLEX 8000, FLEX 10K, ACEX 1K, APEX 20K, Mercury |
| Niveau MSL | — | 1 (per Partstack datasheet record) |