EPC1L20 vs EPC1LI20 Comparison

Detailed side-by-side comparison of EPC1L20 by Altera and EPC1LI20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPC1L20 EPC1LI20
Brand Altera Altera
Category Memory ICs Memory ICs
Lifecycle Status Active Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $3.75 $8.50
Memory Type OTP Configuration PROM (Flash) OTP Configuration PROM (EPROM-based)
Memory Size 1 Mbit 1 Mb (1,048,576 bits)
Configuration Clock (max) 8 MHz β€”
Flash Access Time 90 ns (approx.) β€”
Max Read Bandwidth 160 Mbps (16-bit DQ bus) β€”
Interface Serial / FPP configuration + JTAG (IEEE 1149.1) β€”
Supply Voltage 3.3 V (typical) β€”
Programmability One-Time Programmable (OTP) β€”
Package 20-pin PLCC (9x9 mm) 20-pin PLCC (J-lead, 9x9 mm)
Mounting Type Through-Hole / Socket Surface Mount (PLCC socket compatible)
Operating Temperature [DATA_NEEDED: operating temperature range] [DATA_NEEDED: operating temperature range]
JTAG / ISP Support Yes (IEEE 1149.1) β€”
Compatible FPGA Series Stratix, Cyclone, APEX, FLEX, ACEX, LUT-based families β€”
RoHS Status [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS status - original Altera part may be non-RoHS SnPb finish]
Lead-Free [DATA_NEEDED: lead-free status] β€”
Configuration Interface β€” Altera Passive Serial / Altera Active Serial / JTAG (IEEE 1149.1)
Maximum Configuration Clock β€” 8 MHz
Supply Voltage (VCC) β€” 5.0 V (4.75 V to 5.25 V)
Programming Voltage (VPP) β€” 12.75 V (typical, factory-programmed via JTAG)
Pin Count β€” 20
Cascading Support β€” Yes (nCASC pin for multi-device daisy chain)
Endurance β€” OTP (one-time programmable, 1000 erase-equivalent UV cycles for pre-program erase)
JTAG Programming β€” Yes (in-system via IEEE 1149.1)
Compatible FPGA Families β€” FLEX 8000, FLEX 10K, ACEX 1K, APEX 20K, Mercury
MSL Level β€” 1 (per Partstack datasheet record)

Datasheets & Resources

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