EPC1LC120 vs EPC1LC20-WCEC52 Comparaison
Comparaison détaillée côte à côte de EPC1LC120 par Altera et EPC1LC20-WCEC52 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC1LC120 | EPC1LC20-WCEC52 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | Memory ICs | Memory ICs |
| Statut du cycle de vie | Actif | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,30 | $7,45 |
| Type de mémoire | Serial Configuration Memory (Flash-based, non-volatile) | OTP Configuration PROM (Anti-fuse) |
| Memory Density | 1 Mbit | — |
| Serial Clock Frequency (DCLK) | 8 MHz | — |
| Supported FPGA Families | APEX 20K, ACEX 1K, Cyclone, MAX, Mercury, Stratix-class | — |
| Interface | Altera / Intel proprietary FPGA-configuration serial bus (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) | Serial (Altera FPP/PS configuration protocol) |
| Boîtier | LQFP-120 (Low-profile Quad Flat Pack) | 20-pin PLCC (J-lead, through-hole, 9x9 mm) |
| Type de montage | Surface Mount | — |
| Plage de température de fonctionnement | [DATA_NEEDED: operating temperature range] | — |
| Tension d'alimentation | [DATA_NEEDED: VCC range] | — |
| Programming | Factory / JTAG via Altera programming tools | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Niveau MSL | [DATA_NEEDED: MSL rating] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: lead-free status] |
| Configuration Mode | Serial configuration of SRAM-based FPGAs | — |
| Compatible Bitstream Width | Serial | — |
| Taille de mémoire | — | 1 Mbit (1,048,576 bits) |
| Organisation de la mémoire | — | 212,942 x 1 bit |
| Configuration Clock (DCLK) | — | 8 MHz maximum |
| Supply Voltage (VCC) | — | 3.3 V |
| I/O Voltage Tolerance | — | 5.0 V (FPGA interface) |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Programmability | — | One-Time Programmable (OTP) |
| Température de fonctionnement | — | -40C to +85C (industrial) |
| Package Mounting | — | Through-hole (also accepts PLCC socket) |
| Compatible FPGA Families | — | Cyclone, Stratix, APEX, ACEX, MAX series |
| Programming Interface | — | JTAG (IEEE Std 1149.1) ISP |
| Nombre de broches | — | 20 |
| Statut du cycle de vie | — | Obsolete (recommended replacement: EPCQ family or newer serial config devices) |