EPC1LC20C vs EPC2LC20 Comparaison
Comparaison détaillée côte à côte de EPC1LC20C par Altera et EPC2LC20 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC1LC20C | EPC2LC20 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | Memory ICs |
| Statut du cycle de vie | NRND | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $7,40 | $7,20 |
| Type de mémoire | Serial Configuration Flash | Non-volatile configuration PROM |
| Taille de mémoire | 1 Mbit (1,048,576 bits) | 1.6 Mbit |
| Configuration Clock (DCLK) | 8 MHz maximum | — |
| Interface | Serial (DATA/DCLK) + JTAG (IEEE 1149.1) | — |
| Tension d'alimentation | 3.3 V or 5.0 V | — |
| Programmability | In-system via JTAG | — |
| Cascading Support | Yes (nCS, CS pins) | — |
| Boîtier | 20-pin LCC (Leadless Chip Carrier) | 20-pin PLCC (J-lead, 9x9 mm) |
| Type de montage | Surface Mount (ceramic) | Surface Mount |
| Température de fonctionnement | -40C to +85C (industrial) | -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] |
| Compatible FPGA Families | FLEX 10K, ACEX 1K, APEX 20K | — |
| JTAG Pins | TCK, TMS, TDI, TDO | — |
| Configuration Mode | Slave-serial (FPGA-master) | — |
| Niveau MSL | MSL3 (ceramic, floor life 168 hours) | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | Non-Compliant (original Altera Pb-containing part) |
| Configuration Interface | — | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE |
| Programming Interface | — | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant |
| Supply Voltage VCC | — | 3.0 V to 3.6 V (3.3-V operation) |
| ISP Voltage Range | — | 5.0 V or 3.3 V |
| Supported FPGA Families | — | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 |
| Cascade Support | — | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams |
| Lead-Free Version | — | EPC2LC20N available as lead-free equivalent |
| Programming Support | — | Altera Programming Unit (APU), Quartus II, JTAG programmer |
| Boundary-Scan | — | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG |