EPC1LC20C vs EPC2LC20 Comparación
Comparación detallada lado a lado de EPC1LC20C por Altera y EPC2LC20 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPC1LC20C | EPC2LC20 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | Memory ICs |
| Estado del ciclo de vida | NRND | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $7,40 | $7,20 |
| Tipo de memoria | Serial Configuration Flash | Non-volatile configuration PROM |
| Tamaño de memoria | 1 Mbit (1,048,576 bits) | 1.6 Mbit |
| Configuration Clock (DCLK) | 8 MHz maximum | — |
| Interfaz | Serial (DATA/DCLK) + JTAG (IEEE 1149.1) | — |
| Tensión de alimentación | 3.3 V or 5.0 V | — |
| Programmability | In-system via JTAG | — |
| Cascading Support | Yes (nCS, CS pins) | — |
| Encapsulado | 20-pin LCC (Leadless Chip Carrier) | 20-pin PLCC (J-lead, 9x9 mm) |
| Tipo de montaje | Surface Mount (ceramic) | Surface Mount |
| Temperatura de funcionamiento | -40C to +85C (industrial) | -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] |
| Compatible FPGA Families | FLEX 10K, ACEX 1K, APEX 20K | — |
| JTAG Pins | TCK, TMS, TDI, TDO | — |
| Configuration Mode | Slave-serial (FPGA-master) | — |
| Nivel MSL | MSL3 (ceramic, floor life 168 hours) | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | Non-Compliant (original Altera Pb-containing part) |
| Configuration Interface | — | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE |
| Programming Interface | — | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant |
| Supply Voltage VCC | — | 3.0 V to 3.6 V (3.3-V operation) |
| ISP Voltage Range | — | 5.0 V or 3.3 V |
| Supported FPGA Families | — | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 |
| Cascade Support | — | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams |
| Lead-Free Version | — | EPC2LC20N available as lead-free equivalent |
| Programming Support | — | Altera Programming Unit (APU), Quartus II, JTAG programmer |
| Boundary-Scan | — | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG |