EPC1LC20N vs EPC1LC20U Comparaison
Comparaison détaillée côte à côte de EPC1LC20N par Intel et EPC1LC20U par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC1LC20N | EPC1LC20U |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | Memory ICs | Memory ICs |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $8,40 | $9,75 |
| Type de mémoire | OTP Configuration PROM (EPROM-based) | OTP (One-Time-Programmable) Configuration PROM |
| Taille de mémoire | 1 Mbit | — |
| Programmable Type | OTP (One-Time Programmable) | — |
| Configuration Clock Frequency | 16.7 MHz | — |
| Supply Voltage - VCCINT | 4.75 V to 5.25 V | — |
| Supply Voltage - VCCIO | 3.0 V to 3.6 V | — |
| Température de fonctionnement | 0C to +70C (Commercial) | [DATA_NEEDED: industrial/commercial grade range] |
| Boîtier / Format | 20-LCC (J-Lead), PLCC-20 | — |
| Package Dimensions | 9 mm x 9 mm | — |
| Type de montage | Surface Mount | Surface Mount |
| Packaging | Tube | — |
| Configuration Interface | Serial (DATA, DCLK, nCONFIG, nSTATUS) | Altera Serial Configuration (4-wire) |
| Supported FPGA Families | Altera FLEX, APEX, ACEX, Mercury | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | Compliant (Pb-free finish, "U" suffix) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Memory Density | — | 1 Mbit |
| Maximum DCLK Frequency | — | 8 MHz |
| Boîtier | — | 20-pin PLCC (9x9 mm) |
| Operating Voltage (VCC) | — | 3.3 V typical [DATA_NEEDED: full range] |
| Configuration Time | — | [DATA_NEEDED: depends on bitstream length and DCLK] |
| Cascading Support | — | Yes (multi-PROM daisy-chain for larger bitstreams) |
| Programming Method | — | Altera APU / third-party JTAG programmer |
| Lead-Free (Pb-free) Finish | — | Yes ("U" suffix) |
| Compatibility | — | Altera SRAM-based LUT FPGAs (APEX, FLEX, ACEX, Cyclone, Stratix families) |
| Niveau MSL | — | [DATA_NEEDED] |