EPC1LI20 vs EPC1PC8CC Comparaison
Comparaison détaillée côte à côte de EPC1LI20 par Altera et EPC1PC8CC par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC1LI20 | EPC1PC8CC |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | Memory ICs | Memory ICs |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $8,50 | $9,95 |
| Type de mémoire | OTP Configuration PROM (EPROM-based) | EPROM (OTP, UV-erasable window optional) |
| Taille de mémoire | 1 Mb (1,048,576 bits) | 1 Mbit (1,048,576 bits) |
| Configuration Interface | Altera Passive Serial / Altera Active Serial / JTAG (IEEE 1149.1) | Altera Passive Serial (PS), 4-wire (nSTATUS, nCONFIG, DCLK, DATA0) |
| Maximum Configuration Clock | 8 MHz | — |
| Supply Voltage (VCC) | 5.0 V (4.75 V to 5.25 V) | — |
| Programming Voltage (VPP) | 12.75 V (typical, factory-programmed via JTAG) | — |
| Boîtier | 20-pin PLCC (J-lead, 9x9 mm) | PDIP-8 (Plastic DIP, 8-pin, 0.1" pitch) |
| Nombre de broches | 20 | 8 |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | — |
| Cascading Support | Yes (nCASC pin for multi-device daisy chain) | — |
| Endurance | OTP (one-time programmable, 1000 erase-equivalent UV cycles for pre-program erase) | — |
| JTAG Programming | Yes (in-system via IEEE 1149.1) | — |
| Compatible FPGA Families | FLEX 8000, FLEX 10K, ACEX 1K, APEX 20K, Mercury | ACEX 1K, APEX 20K, APEX II, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, FLEX 8000, MAX 7000B/AE/S, MAX 9000, Mercury, Stratix, Stratix II, Arria |
| Type de montage | Surface Mount (PLCC socket compatible) | Through-Hole (DIP socketable) |
| Niveau MSL | 1 (per Partstack datasheet record) | 1 (unlimited floor life) |
| Statut RoHS | [DATA_NEEDED: RoHS status - original Altera part may be non-RoHS SnPb finish] | — |
| Fonction | — | FPGA Configuration PROM |
| Supply Voltage VCC | — | 3.0 V to 3.6 V (typical 3.3 V) |
| Maximum DCLK Frequency | — | 17.6 MHz (17.6 Mb/s effective bitstream rate) |
| Plage de température de fonctionnement | — | [DATA_NEEDED: full industrial range from datasheet] |
| Cascade Support | — | Not supported in DIP-8 package (nCASC pin not exposed) |
| Programming Interface | — | JTAG via Altera Quartus / Quartus Prime ByteBlaster |
| Error Detection | — | Built-in CRC during configuration transfer |
| Lead-Free / RoHS | — | Not lead-free (legacy Altera/Intel PC8 suffix is Sn-Pb finish); RoHS non-compliant variant |