EPC27TC32N vs EPC2-TC32 Comparaison
Comparaison détaillée côte à côte de EPC27TC32N par Altera et EPC2-TC32 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC27TC32N | EPC2-TC32 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | Memory ICs |
| Statut du cycle de vie | Unknown | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $0,00 | $15,90 |
| Product Type | Configuration device for SRAM-based LUT devices | — |
| Manufacturer | Altera | — |
| Target Logic Type | SRAM-based LUT devices | — |
| Configuration Memory Capacity | [DATA_NEEDED: configuration memory capacity] | — |
| Configuration Interface | [DATA_NEEDED: configuration interface] | — |
| Programming Mode | [DATA_NEEDED: programming mode] | — |
| Supported FPGA Families | [DATA_NEEDED: supported FPGA families] | Stratix I/II, Cyclone I/II, APEX 20K/II, Mercury, ACEX 1K, FLEX 10K |
| Operating Voltage | [DATA_NEEDED: operating voltage] | — |
| Clock Frequency | [DATA_NEEDED: clock frequency] | — |
| Configuration Startup Time | [DATA_NEEDED: configuration startup time] | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature] | — |
| Boîtier | [DATA_NEEDED: package] | 32-pin TQFP (7x7 mm) |
| Nombre de broches | [DATA_NEEDED: pin count] | — |
| Type de montage | [DATA_NEEDED: mounting type] | Surface Mount |
| Package Dimensions | [DATA_NEEDED: package dimensions] | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status - datasheet does not specify in retrieved snippet] |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Lead-Free Status | [DATA_NEEDED: lead-free status] | — |
| Halogen-Free Status | [DATA_NEEDED: halogen-free status] | — |
| Conflict-Mineral Status | [DATA_NEEDED: conflict-mineral status] | — |
| Type de mémoire | — | EPROM (OTP/UV-erasable configuration PROM) |
| Taille de mémoire | — | 1.6 Mbit |
| Type d'interface | — | Serial |
| Organisation de la mémoire | — | Serial bitstream output |
| Programmability | — | In-System Programmable (ISP) via JTAG (IEEE 1149.1) |
| Tension d'alimentation | — | 3.3 V |
| Plage de température de fonctionnement | — | 0C to +70C (Commercial) |
| Configuration Mode | — | Serial (FPP/MSD via FPGA master/slave) |
| Output Control | — | OE and nCS gating internal tri-state buffer |
| Internal Oscillator | — | Yes (drives address counter) |
| Niveau MSL | — | MSL 3 (168 hours) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |