EPC27TC32N vs EPC2-TC32 对比
详细并排对比 EPC27TC32N 出自 Altera 和 EPC2-TC32 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPC27TC32N | EPC2-TC32 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | Memory ICs |
| 生命周期状态 | Unknown | 最后采购期 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $0.00 | $15.90 |
| Product Type | Configuration device for SRAM-based LUT devices | — |
| Manufacturer | Altera | — |
| Target Logic Type | SRAM-based LUT devices | — |
| Configuration Memory Capacity | [DATA_NEEDED: configuration memory capacity] | — |
| Configuration Interface | [DATA_NEEDED: configuration interface] | — |
| Programming Mode | [DATA_NEEDED: programming mode] | — |
| Supported FPGA Families | [DATA_NEEDED: supported FPGA families] | Stratix I/II, Cyclone I/II, APEX 20K/II, Mercury, ACEX 1K, FLEX 10K |
| Operating Voltage | [DATA_NEEDED: operating voltage] | — |
| Clock Frequency | [DATA_NEEDED: clock frequency] | — |
| Configuration Startup Time | [DATA_NEEDED: configuration startup time] | — |
| 工作温度 | [DATA_NEEDED: operating temperature] | — |
| 封装 | [DATA_NEEDED: package] | 32-pin TQFP (7x7 mm) |
| 引脚数量 | [DATA_NEEDED: pin count] | — |
| 安装类型 | [DATA_NEEDED: mounting type] | Surface Mount |
| Package Dimensions | [DATA_NEEDED: package dimensions] | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status - datasheet does not specify in retrieved snippet] |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Lead-Free Status | [DATA_NEEDED: lead-free status] | — |
| Halogen-Free Status | [DATA_NEEDED: halogen-free status] | — |
| Conflict-Mineral Status | [DATA_NEEDED: conflict-mineral status] | — |
| 存储器类型 | — | EPROM (OTP/UV-erasable configuration PROM) |
| 存储容量 | — | 1.6 Mbit |
| 接口类型 | — | Serial |
| 存储组织 | — | Serial bitstream output |
| Programmability | — | In-System Programmable (ISP) via JTAG (IEEE 1149.1) |
| 电源电压 | — | 3.3 V |
| 工作温度范围 | — | 0C to +70C (Commercial) |
| Configuration Mode | — | Serial (FPP/MSD via FPGA master/slave) |
| Output Control | — | OE and nCS gating internal tri-state buffer |
| Internal Oscillator | — | Yes (drives address counter) |
| MSL 等级 | — | MSL 3 (168 hours) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |