EPC2C20 vs EPC1C20 Comparaison
Comparaison détaillée côte à côte de EPC2C20 par Altera et EPC1C20 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC2C20 | EPC1C20 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $0,00 | $8,20 |
| Manufacturer | Altera | Intel (formerly Altera) |
| MPN | EPC2C20 | — |
| Device Type | Configuration device integrated circuit | — |
| Primary Function | Configuration of SRAM-based lookup-table devices | — |
| Configuration Architecture | Single-device configuration solution | — |
| Architecture Block 1 | Configuration controller | — |
| Architecture Block 2 | Flash memory | — |
| Memory Technology | Flash memory | — |
| Supported Device Class | SRAM-based LUT devices | — |
| Configuration Mode | [DATA_NEEDED: configuration mode] | — |
| Memory Density | [DATA_NEEDED: memory density] | — |
| Configuration Data Interface | [DATA_NEEDED: configuration data interface] | — |
| Operating Voltage | [DATA_NEEDED: operating voltage] | — |
| Configuration Clock Frequency | [DATA_NEEDED: configuration clock frequency] | — |
| Boîtier | [DATA_NEEDED: package] | 20-pin PLCC (J-lead) |
| Nombre de broches | [DATA_NEEDED: pin count] | — |
| Plage de température de fonctionnement | [DATA_NEEDED: operating temperature range] | -40 C to +85 C (industrial) [DATA_NEEDED: confirm exact grade] |
| Statut RoHS | [DATA_NEEDED: RoHS status] | unknown |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Product Type | — | Enhanced Configuration (EPC) Device / Serial Configuration PROM |
| Supported Altera Families | — | APEX II, APEX 20K, Cyclone, ACEX 1K, Mercury, Excalibur |
| Configuration Interface | — | Altera Passive Serial (PS), 4-pin (nSTATUS, nCONFIG, CONF_DONE, DATA, DCLK) |
| Supply Voltage (VCCINT) | — | 5.0 V nominal |
| I/O Voltage (VCCIO) | — | 3.3 V or 5.0 V |
| Programming Interface | — | JTAG (IEEE Std 1149.1) in-system programming |
| Memory Cell Technology | — | CMOS EPROM (non-volatile, one-time or reprogrammable) |
| Configuration Bit Capacity | — | [DATA_NEEDED: configuration bit capacity in Mb] |
| Type de montage | — | Surface Mount (PLCC socket compatible for through-hole prototyping) |
| Lead-Free / Halogen-Free | — | unknown |
| Statut du cycle de vie | — | Obsolete (NRND by Altera; supported stock only) |
| Configuration Clock Source | — | Target FPGA supplies DCLK (EPC is slave) |
| In-System Programmability | — | Yes (via JTAG) |