EPC2C20 vs EPC1C20 तुलना
विस्तृत दोनों ओर की तुलना EPC2C20 द्वारा Altera और EPC1C20 द्वारा Intel. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EPC2C20 | EPC1C20 |
|---|---|---|
| ब्रांड | Altera | Intel |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | सक्रिय | Obsolete |
| Manufacturer | Altera | Intel (formerly Altera) |
| MPN | EPC2C20 | — |
| Device Type | Configuration device integrated circuit | — |
| Primary Function | Configuration of SRAM-based lookup-table devices | — |
| Configuration Architecture | Single-device configuration solution | — |
| Architecture Block 1 | Configuration controller | — |
| Architecture Block 2 | Flash memory | — |
| Memory Technology | Flash memory | — |
| Supported Device Class | SRAM-based LUT devices | — |
| Configuration Mode | [DATA_NEEDED: configuration mode] | — |
| Memory Density | [DATA_NEEDED: memory density] | — |
| Configuration Data Interface | [DATA_NEEDED: configuration data interface] | — |
| Operating Voltage | [DATA_NEEDED: operating voltage] | — |
| Configuration Clock Frequency | [DATA_NEEDED: configuration clock frequency] | — |
| पैकेज | [DATA_NEEDED: package] | 20-pin PLCC (J-lead) |
| पिन काउंट | [DATA_NEEDED: pin count] | — |
| ऑपरेटिंग तापमान रेंज | [DATA_NEEDED: operating temperature range] | -40 C to +85 C (industrial) [DATA_NEEDED: confirm exact grade] |
| RoHS स्थिति | [DATA_NEEDED: RoHS status] | unknown |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Product Type | — | Enhanced Configuration (EPC) Device / Serial Configuration PROM |
| Supported Altera Families | — | APEX II, APEX 20K, Cyclone, ACEX 1K, Mercury, Excalibur |
| Configuration Interface | — | Altera Passive Serial (PS), 4-pin (nSTATUS, nCONFIG, CONF_DONE, DATA, DCLK) |
| Supply Voltage (VCCINT) | — | 5.0 V nominal |
| I/O Voltage (VCCIO) | — | 3.3 V or 5.0 V |
| Programming Interface | — | JTAG (IEEE Std 1149.1) in-system programming |
| Memory Cell Technology | — | CMOS EPROM (non-volatile, one-time or reprogrammable) |
| Configuration Bit Capacity | — | [DATA_NEEDED: configuration bit capacity in Mb] |
| माउंटिंग प्रकार | — | Surface Mount (PLCC socket compatible for through-hole prototyping) |
| Lead-Free / Halogen-Free | — | unknown |
| लाइफसाइकिल स्थिति | — | Obsolete (NRND by Altera; supported stock only) |
| Configuration Clock Source | — | Target FPGA supplies DCLK (EPC is slave) |
| In-System Programmability | — | Yes (via JTAG) |