EPC2LC2QN vs EPC2LI20N Comparaison
Comparaison détaillée côte à côte de EPC2LC2QN par Altera et EPC2LI20N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC2LC2QN | EPC2LI20N |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | Memory ICs | Memory ICs |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $15,20 | $5,10 |
| Product Type | FPGA Configuration Device | — |
| Configuration Memory Size | 2 Mb | — |
| Target Device Family | SRAM-Based LUT FPGAs (APEX II, Cyclone, Stratix) | — |
| Core Supply Voltage | 3.3 V | — |
| I/O Supply Voltage | 3.3 V | — |
| Température de fonctionnement | 0°C to +70°C (Commercial) | [DATA_NEEDED: operating temperature range] |
| Boîtier | 100-pin PQFP | — |
| Type de montage | Surface Mount | Surface Mount |
| Configuration Interface | 4-wire Serial (DATA, DCLK, nCONFIG, nSTATUS) | — |
| Programming Interface | JTAG (IEEE 1149.1) | — |
| Bitstream Compression | Supported (Altera-compressed format) | — |
| Multi-Device Daisy-Chain Support | Yes (up to 8 FPGAs) | — |
| In-System Programmability | Yes | — |
| Bitstream Programming Cycles | [DATA_NEEDED: minimum endurance cycles] | — |
| Statut RoHS | Compliant | [DATA_NEEDED: RoHS status] |
| Lead-Free | Yes | — |
| Niveau MSL | [DATA_NEEDED: MSL rating] | — |
| Country of Origin | [DATA_NEEDED: COO] | — |
| Type de mémoire | — | Non-volatile configuration PROM (Flash) |
| Taille de mémoire | — | 1.6 Mbit |
| Programmable Type | — | In System Programmable (ISP via JTAG) |
| Configuration Mode | — | Serial |
| Maximum Configuration Frequency | — | 10 MHz |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V |
| Supply Voltage (VCCIO) | — | 4.5 V to 5.5 V |
| Boîtier / Format | — | 20-PLCC (J-Lead), 9x9 mm |
| Packaging | — | Tube |
| Supported FPGA Series | — | ACEX 1K, APEX II, Cyclone, Stratix II |
| JTAG Interface | — | IEEE 1149.1 boundary scan (TCK/TDI/TMS/TDO) |
| Configuration Pins | — | nCS, DCLK, DATA, nCONFIG, nSTATUS, CONF_DONE |