EPC8QI100N vs EPC8QI100 Comparaison
Comparaison détaillée côte à côte de EPC8QI100N par Altera et EPC8QI100 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC8QI100N | EPC8QI100 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | EEPROM | Memory ICs |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $16,90 | $10,85 |
| Manufacturer | Altera (Intel) | — |
| Part Family | EPC8 (Enhanced Configuration) | — |
| Device Type | Configuration PROM for SRAM-based FPGAs | — |
| Taille de mémoire | 8 Mbit (8,388,608 bits) | 8 Mbit |
| Programmable Type | In System Programmable (Flash) | — |
| Configuration Interface | Altera serial (4-wire: DATA, DCLK, nCS, nINIT_CONF) | — |
| Maximum Configuration Clock | 50 MHz | — |
| On-Chip Decompression | Yes (Altera compression algorithm) | — |
| Supply Voltage (VCC) | 3.0 V to 3.6 V | — |
| Température de fonctionnement | -40 °C to +85 °C (Industrial) | -40C to +85C (industrial) |
| Boîtier | 100-PQFP / 100-BQFP (20 x 14 mm) | 100-PQFP (20 x 14 mm) |
| Nombre de broches | 100 | — |
| Type de montage | Surface Mount | Surface Mount |
| Lead-Free / RoHS | Yes (per distributor listings) | — |
| JTAG (IEEE 1149.1) ISP | Supported | — |
| Multi-Device Daisy-Chain | Supported | — |
| Target FPGA Families | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX | — |
| Packaging | Tray | — |
| Type de mémoire | — | Flash (NOR, Enhanced Configuration PROM) |
| Supply Voltage (Core) | — | 3.3 V |
| Supply Voltage (I/O) | — | 3.3 V |
| Interface | — | Altera FPGA configuration serial/parallel (FPP) + JTAG (IEEE 1149.1) |
| In-System Programmability | — | IEEE Std. 1532 compliant |
| Programming Language | — | Jam STAPL |
| Boundary Scan | — | JTAG boundary-scan test supported |
| Data Compression | — | Yes (increases effective capacity) |
| Configuration Controller | — | On-chip, dedicated to Altera FPGAs |
| Initiate-Configuration Pin | — | nINIT_CONF (private JTAG instruction) |
| Compatible FPGAs | — | Stratix, Stratix II, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, Cyclone, Cyclone II, Arria GX, Stratix GX, Stratix II GX |
| Statut RoHS | — | Non-compliant (legacy PQFP, lead-bearing) |