EPF10K200SFC484-2X vs EPF10K200SFC484-2N Comparaison
Comparaison détaillée côte à côte de EPF10K200SFC484-2X par Intel et EPF10K200SFC484-2N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPF10K200SFC484-2X | EPF10K200SFC484-2N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $171,00 | $95,00 |
| Series | FLEX 10KS | — |
| Family | FLEX 10K | FLEX 10KE |
| Number of Logic Elements / Cells | 9984 | — |
| Number of LABs / CLBs | 1248 | — |
| Total RAM Bits | 98304 | — |
| Number of Gates | 200000 (typical) | — |
| Number of I/O | 369 | — |
| Core Voltage - Supply | 2.375 V to 2.625 V | — |
| Operating Frequency (max) | 250 MHz (family-typical, -2 speed grade) | — |
| Température de fonctionnement | 0C to +70C (commercial) | 0°C to 70°C (Commercial) |
| Boîtier / Format | 484-BBGA (FineLine BGA) | — |
| Supplier Device Package | 484-FBGA (23 x 23 mm, 1.0 mm pitch) | — |
| Type de montage | Surface Mount | Surface Mount |
| Technology | CMOS, SRAM-based configuration | — |
| Configuration Memory | External serial (EPC1/EPC2 family compatible) | — |
| JTAG Support | IEEE 1149.1-1990 boundary-scan | — |
| Process Technology | [DATA_NEEDED: process node nm] | 0.22 µm CMOS |
| Statut RoHS | [DATA_NEEDED: rohs status] | — |
| Logic Elements / Cells | — | 9,984 |
| Gate Count | — | 200,000 |
| Logic Array Blocks (LABs) | — | 1,248 |
| Embedded RAM Bits | — | 98,304 (96 Kbit) |
| User I/O Pins | — | 369 |
| Number of I/Os (alt spec) | — | 470 (per digchip datasheet summary) |
| Core Supply Voltage | — | 2.375 V to 2.625 V (2.5 V nominal) |
| Internal Performance | — | 200 MHz |
| Propagation Delay | — | 0.4 ns |
| Boîtier | — | 484-FBGA FineLine BGA, 23 x 23 mm, 1.0 mm pitch |
| Programming Interface | — | JTAG (IEEE 1149.1), SRAM configuration |
| I/O Standard Support | — | 5 V-tolerant, MultiVolt (1.8 V / 2.5 V / 3.3 V) |
| Logic Family | — | CMOS |
| Compliance / Lead Status | — | [DATA_NEEDED: RoHS status] |