EPF10K200SFC672-1 vs EPF10K200SFC672-2 Comparaison
Comparaison détaillée côte à côte de EPF10K200SFC672-1 par Altera et EPF10K200SFC672-2 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPF10K200SFC672-1 | EPF10K200SFC672-2 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $138,75 | $320,00 |
| Series | FLEX 10KE | FLEX 10KE |
| Family | FLEX 10KE (FLEX-10KS) | — |
| Logic Elements / Cells | 9984 | — |
| Total RAM Bits | 98304 | — |
| Number of LABs/CLBs | 1248 | — |
| Number of User I/Os | 470 | — |
| Number of Gates | 200K system gates | — |
| Core Voltage (VCCINT) | 2.5 V | — |
| I/O Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (multi-volt) | — |
| Maximum Operating Frequency | 250 MHz | 200 MHz |
| Propagation Delay | 0.4 ns | — |
| Process Technology | 0.22 µm CMOS, SRAM-based | 0.22 µm CMOS |
| Package Type | 672-ball FBGA (FineLine BGA), 45 x 45 mm, 1.27 mm pitch | — |
| Température de fonctionnement | 0 °C to +70 °C (Commercial) | 0 °C to +70 °C (Commercial) |
| Programming Interface | JTAG (IEEE 1149.1) + serial/parallel passive configuration | — |
| Embedded Array Blocks (EABs) | 12 | — |
| Speed Grade | -1 | -2 |
| Type de montage | Surface Mount | — |
| Niveau MSL | [DATA_NEEDED: MSL level] | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Logic Elements | — | 9,984 |
| System Gates | — | 200,000 |
| Logic Array Blocks (LABs) | — | 1,248 |
| User I/O Pins | — | 470 |
| Embedded Memory (bits) | — | 98,304 |
| Core Supply Voltage | — | 2.5 V (2.375 V to 2.625 V) |
| I/O Supply Voltage | — | MultiVolt 2.5 V / 3.3 V / 5.0 V |
| Internal Propagation Delay | — | 0.4 ns |
| Boîtier | — | 672-pin FineLine BGA (FBGA), 45 × 45 mm, 1.27 mm pitch |
| Configuration Method | — | SRAM-based, passive parallel asynchronous |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |
| On-chip PLL | — | Yes |