EPF10K200SFC672-1 vs EPF10K200SFC672-2 Comparação
Comparação detalhada lado a lado de EPF10K200SFC672-1 por Altera e EPF10K200SFC672-2 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EPF10K200SFC672-1 | EPF10K200SFC672-2 |
|---|---|---|
| Marca | Altera | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | NRND |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $138,75 | $320,00 |
| Series | FLEX 10KE | FLEX 10KE |
| Family | FLEX 10KE (FLEX-10KS) | — |
| Logic Elements / Cells | 9984 | — |
| Total RAM Bits | 98304 | — |
| Number of LABs/CLBs | 1248 | — |
| Number of User I/Os | 470 | — |
| Number of Gates | 200K system gates | — |
| Core Voltage (VCCINT) | 2.5 V | — |
| I/O Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (multi-volt) | — |
| Maximum Operating Frequency | 250 MHz | 200 MHz |
| Propagation Delay | 0.4 ns | — |
| Process Technology | 0.22 µm CMOS, SRAM-based | 0.22 µm CMOS |
| Package Type | 672-ball FBGA (FineLine BGA), 45 x 45 mm, 1.27 mm pitch | — |
| Temperatura de operação | 0 °C to +70 °C (Commercial) | 0 °C to +70 °C (Commercial) |
| Programming Interface | JTAG (IEEE 1149.1) + serial/parallel passive configuration | — |
| Embedded Array Blocks (EABs) | 12 | — |
| Speed Grade | -1 | -2 |
| Tipo de montagem | Surface Mount | — |
| Nível MSL | [DATA_NEEDED: MSL level] | — |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Logic Elements | — | 9,984 |
| System Gates | — | 200,000 |
| Logic Array Blocks (LABs) | — | 1,248 |
| User I/O Pins | — | 470 |
| Embedded Memory (bits) | — | 98,304 |
| Core Supply Voltage | — | 2.5 V (2.375 V to 2.625 V) |
| I/O Supply Voltage | — | MultiVolt 2.5 V / 3.3 V / 5.0 V |
| Internal Propagation Delay | — | 0.4 ns |
| Encapsulamento | — | 672-pin FineLine BGA (FBGA), 45 × 45 mm, 1.27 mm pitch |
| Configuration Method | — | SRAM-based, passive parallel asynchronous |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |
| On-chip PLL | — | Yes |