EPF10K200SRC240-3 vs EPF10K200SRC240-3N Comparaison
Comparaison détaillée côte à côte de EPF10K200SRC240-3 par Intel et EPF10K200SRC240-3N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPF10K200SRC240-3 | EPF10K200SRC240-3N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $132,00 | $162,00 |
| Family | FLEX 10KE | FLEX 10KE |
| Series | FLEX-10KS | — |
| Logic Elements / Cells | 9984 | — |
| Total System Gates | 200,000 | — |
| Total RAM Bits | 98,304 | — |
| Number of LABs/CLBs | 1248 | — |
| Number of I/Os | 470 | — |
| Number of DLLs | 4 | — |
| Boîtier | 240-BFQFP Exposed Pad (RQFP-240) | 240-pin RQFP (Power QFP) with exposed pad, 34.6 x 34.6 mm, 0.5 mm pitch |
| Package Dimensions | 34.60 x 34.6 mm, 0.5 mm pitch | — |
| Process Technology | 0.22 um CMOS | 0.22 µm CMOS SRAM |
| Core Voltage (VCCINT) | 2.5 V | — |
| I/O Voltage (VCCIO) | MultiVolt (2.5 V / 3.3 V / 5.0 V tolerant) | — |
| Maximum Internal Frequency | 166.67 MHz | — |
| Propagation Delay | 0.4 ns | — |
| Température de fonctionnement | 0 C to 70 C (Commercial) | 0 °C to +70 °C (Commercial) |
| Type de montage | Surface Mount | Surface Mount |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Typical System Gates | — | 200,000 |
| Logic Elements (LEs) | — | 9,984 |
| Maximum Logic Elements | — | 9,984 |
| Embedded Array Blocks (EABs) | — | 24 |
| Maximum User RAM Bits | — | 98,304 |
| Logic Array Blocks (LABs) | — | 1,248 |
| User I/Os | — | 470 (effective); 182 user pins per RQFP-240 with the rest assigned to dedicated functions |
| Propagation Delay (tPD) | — | 0.40 ns |
| Internal Operating Frequency | — | 166.67 MHz |
| Core Supply Voltage | — | 2.5 V |
| MultiVolt I/O Support | — | 2.5 V and 3.3 V interfaces |
| JTAG Support | — | IEEE Std 1149.1 Boundary-Scan (contributes up to 31,250 gates of test logic) |
| Configuration Method | — | SRAM-based; requires external configuration device (e.g., EPC2) for power-up loading |
| Speed Grade | — | -3 (commercial) |