EPF10K20RC240-3N vs EPF10K20RC240-3 Comparaison
Comparaison détaillée côte à côte de EPF10K20RC240-3N par Altera et EPF10K20RC240-3 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPF10K20RC240-3N | EPF10K20RC240-3 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $23,10 | $21,20 |
| Series | FLEX 10K | FLEX-10K® |
| Family | Embedded Programmable Logic Device (EPLD) | FLEX 10K |
| Logic Cells / Elements | 1152 | — |
| Total Gates | 20,000 (typical usable) | — |
| Logic Capacity (typical) | 12,888 | — |
| Logic Array Blocks (LABs) | 144 | 189 |
| User I/O Pins | 189 | — |
| Embedded Array Blocks (EABs) | 6 (per family architecture) | 6 (2 Kbit each) |
| Nombre de broches | 240 | — |
| Package Type | 240-RQFP (HFQFP, exposed pad) | — |
| Package Code | HFQFP / RQFP | — |
| Type de montage | Surface Mount (gull wing) | Surface Mount |
| Tension d'alimentation | 5 V | — |
| Technology / Process | 0.42 µm CMOS | — |
| Maximum Internal Frequency | 125 MHz | 125 MHz |
| Propagation Delay | 0.4 ns (typical) | — |
| Speed Grade | -3 | -3 |
| Température de fonctionnement | 0 °C to +70 °C (commercial) | 0 °C to +70 °C (Commercial) |
| Programming Interface | JTAG (IEEE 1149.1), ByteBlaster / MasterBlaster / ByteBlasterMV | — |
| Configuration Memory | SRAM (volatile, re-programmable) | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | unknown (legacy Altera part, likely non-RoHS) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Typical Gates | — | 20,000 |
| Logic Elements (LEs) | — | 12,288 |
| Flip-Flops | — | 1,152 |
| Total EAB RAM | — | 12 Kbits |
| User I/Os | — | 470 (max per package) |
| Boîtier | — | 240-BFQFP Exposed Pad (RQFP-240) |
| Process Technology | — | 0.42 µm CMOS, 5 metal layers |
| Core Supply Voltage (VCCINT) | — | 5 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V or 5 V tolerant |
| Propagation Delay (tpd) | — | 0.4 ns |
| Configuration Interface | — | JTAG (IEEE 1149.1) + serial configuration PROM |
| Niveau MSL | — | [DATA_NEEDED: MSL rating] |
| Programming | — | SRAM-based, in-system reconfigurable |