EPF10K50EQC240-3 vs EPF10K50SQC240-3N Comparaison

Comparaison détaillée côte à côte de EPF10K50EQC240-3 par Altera et EPF10K50SQC240-3N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.

Altera
EPF10K50EQC240-3 EPF10K50EQC240-3 - FLEX 10KE FPGA, 50K Gates, 240-PQFP | Altera

EPF10K50EQC240-3 - FLEX 10KE FPGA, 50K Gates, 240-PQFP | Altera

EPF10K50EQC240-3 ⚠ Dernier achat

Comparaison des spécifications

Paramètre EPF10K50EQC240-3 EPF10K50SQC240-3N
Marque Altera Altera
Catégorie FPGA & CPLD FPGA & CPLD
Statut du cycle de vie Dernier achat Obsolete
Statut du stock In Stock In Stock
Prix unitaire (USD) $21,00 $60,00
Family FLEX 10KE FLEX 10KE
Device Type FPGA - Field Programmable Gate Array —
Logic Cells / Elements 2880 2,880
Typical Gate Count 50000 —
Number of LABs/CLBs 360 —
Total RAM Bits 40960 —
Number of I/Os 189 —
Internal Frequency 166.67 MHz —
Propagation Delay 0.6 ns —
Operating Supply Voltage (Core) 2.5 V —
Logic Family CMOS CMOS
Process Technology 0.22 um CMOS 0.22 µm CMOS
Package Type 240-BFQFP (PQFP-240, gull-wing) —
Number of Terminals 240 —
Température de fonctionnement 0 C to +70 C (Commercial) 0 °C to 70 °C (Commercial)
Programming Method In-system via serial configuration EPROM —
Embedded Array Blocks Yes (EABs for RAM/ROM/FIFO) —
Type de montage Surface Mount (PQFP) Surface Mount
Statut RoHS [DATA_NEEDED: RoHS compliance] Compliant (Pb-free N suffix)
Typical Gates — 50,000
System Gates — 40,960
Logic Array Blocks (LABs) — 360
Embedded Array Blocks (EABs) — 12
On-chip EAB Memory — 24 Kbits
User I/Os — 189 (per DigiKey listing); 274 user I/Os (per Digchip listing)
Number of I/Os (per distributor) — 189 (DigiKey / Mouser)
Propagation Delay (tpd) — 0.6 ns
Internal Frequency (Fmax) — 166.67 MHz
Core Supply Voltage (VCCINT) — 2.5 V
I/O Voltage (VCCIO) — MultiVolt: 2.5 V / 3.3 V / 5.0 V tolerant
Boîtier — 240-pin PQFP (Power Quad Flat Pack), 34.60 x 34.6 mm, 0.5 mm pitch
Speed Grade — -3 (faster Fmax)
Lead-Free Finish (N suffix) — Yes
JTAG Boundary Scan — IEEE Std. 1149.1 compliant
Programming Technology — SRAM-based, in-system reconfigurable via JTAG
Design Tool — Altera Quartus II (FLEX 10KE support)

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