EPF10K50EQC240-3 vs EPF10K50SQC240-3N 비교
다음의 상세 나란히 비교: EPF10K50EQC240-3 제조: Altera 및 EPF10K50SQC240-3N 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Altera
EPF10K50SQC240-3N - FLEX 10KE 50K Gates FPGA, 240-PQFP | Altera / Intel
EPF10K50SQC240-3N Obsolete사양 비교
| 파라미터 | EPF10K50EQC240-3 | EPF10K50SQC240-3N |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | 최종 구매 | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $21.00 | $60.00 |
| Family | FLEX 10KE | FLEX 10KE |
| Device Type | FPGA - Field Programmable Gate Array | — |
| Logic Cells / Elements | 2880 | 2,880 |
| Typical Gate Count | 50000 | — |
| Number of LABs/CLBs | 360 | — |
| Total RAM Bits | 40960 | — |
| Number of I/Os | 189 | — |
| Internal Frequency | 166.67 MHz | — |
| Propagation Delay | 0.6 ns | — |
| Operating Supply Voltage (Core) | 2.5 V | — |
| Logic Family | CMOS | CMOS |
| Process Technology | 0.22 um CMOS | 0.22 µm CMOS |
| Package Type | 240-BFQFP (PQFP-240, gull-wing) | — |
| Number of Terminals | 240 | — |
| 동작 온도 | 0 C to +70 C (Commercial) | 0 °C to 70 °C (Commercial) |
| Programming Method | In-system via serial configuration EPROM | — |
| Embedded Array Blocks | Yes (EABs for RAM/ROM/FIFO) | — |
| 실장 유형 | Surface Mount (PQFP) | Surface Mount |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance] | Compliant (Pb-free N suffix) |
| Typical Gates | — | 50,000 |
| System Gates | — | 40,960 |
| Logic Array Blocks (LABs) | — | 360 |
| Embedded Array Blocks (EABs) | — | 12 |
| On-chip EAB Memory | — | 24 Kbits |
| User I/Os | — | 189 (per DigiKey listing); 274 user I/Os (per Digchip listing) |
| Number of I/Os (per distributor) | — | 189 (DigiKey / Mouser) |
| Propagation Delay (tpd) | — | 0.6 ns |
| Internal Frequency (Fmax) | — | 166.67 MHz |
| Core Supply Voltage (VCCINT) | — | 2.5 V |
| I/O Voltage (VCCIO) | — | MultiVolt: 2.5 V / 3.3 V / 5.0 V tolerant |
| 패키지 | — | 240-pin PQFP (Power Quad Flat Pack), 34.60 x 34.6 mm, 0.5 mm pitch |
| Speed Grade | — | -3 (faster Fmax) |
| Lead-Free Finish (N suffix) | — | Yes |
| JTAG Boundary Scan | — | IEEE Std. 1149.1 compliant |
| Programming Technology | — | SRAM-based, in-system reconfigurable via JTAG |
| Design Tool | — | Altera Quartus II (FLEX 10KE support) |