EPF10K50VRC240-4N vs EPF10K50VRC240-4 Comparaison
Comparaison détaillée côte à côte de EPF10K50VRC240-4N par Altera et EPF10K50VRC240-4 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPF10K50VRC240-4N - 50K-Gate FLEX-10K FPGA, 240-RQFP | Intel / Altera
EPF10K50VRC240-4N ObsoleteAltera
EPF10K50VRC240-4 - 50K Gate FLEX-10K FPGA, 240-Pin RQFP | Altera / Intel
EPF10K50VRC240-4 NrndComparaison des spécifications
| Paramètre | EPF10K50VRC240-4N | EPF10K50VRC240-4 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $89,50 | $85,30 |
| Family | FLEX-10K | FLEX-10K |
| Series | FLEX-10K | — |
| Product Type | FPGA - Field Programmable Gate Array | — |
| Logic Family | CMOS | — |
| Typical Gates | 50,000 | 50,000 |
| Logic Cells / Elements | 2,880 | — |
| Logic Array Blocks (LABs) | 360 | 360 |
| Embedded Array Blocks (EABs) | 36 | 10 (each up to 2,048 bits) |
| Embedded Memory (Total RAM Bits) | 20,480 | — |
| Maximum User I/Os | 189 | 189 |
| Number of I/Os | 189 | — |
| Boîtier | 240-BFQFP Exposed Pad (RQFP / RQFP-EP) | 240-pin RQFP (RQFP-240) with exposed pad |
| Package Pin Count | 240 | — |
| Type de montage | Surface Mount | Surface Mount |
| Internal Frequency (typical) | 66.67 MHz | — |
| Propagation Delay | 0.6 ns | — |
| Speed Grade | -4 | -4 |
| Core Supply Voltage | 3.3 V | — |
| Température de fonctionnement | 0 C to 70 C | 0C to +70C (commercial) |
| Niveau MSL | [DATA_NEEDED: MSL Level] | — |
| Statut RoHS | [DATA_NEEDED: RoHS Status] | Non-compliant (legacy SnPb lead frame) |
| Logic Elements (LEs) | — | 2,880 |
| Core Voltage (VCCINT) | — | 3.3 V |
| I/O Voltage (VCCIO) | — | 3.3 V or 5.0 V tolerant |
| Internal Frequency (max) | — | 125 MHz |
| Propagation Delay (per LE) | — | 0.6 ns |
| Configuration Method | — | SRAM, serial/parallel via EPC2/EPC8 PROM |
| Programming Interface | — | JTAG (IEEE 1149.1), ByteBlaster, BitBlaster |
| Lead-Free | — | No (commercial grade is SnPb; -N suffix is lead-free) |