EPF8636ALC84-3 vs EPF8636ALC84-4 Comparaison
Comparaison détaillée côte à côte de EPF8636ALC84-3 par Intel et EPF8636ALC84-4 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPF8636ALC84-3 | EPF8636ALC84-4 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $18,75 | $24,30 |
| Family | FLEX 8000 | FLEX 8000 |
| Usable Gates | 6,000 | — |
| Logic Elements / Cells | 504 | — |
| Logic Array Blocks (LABs) | 63 | — |
| Embedded Array Blocks (EABs) | 6 (2,048 bits each, 12,288 total RAM bits) | — |
| User I/Os | 68 | — |
| Maximum Operating Frequency | 125 MHz | 125 MHz |
| Process Technology | 0.42 µm CMOS, 5-metal | 0.42 µm CMOS SRAM |
| Core Supply Voltage | 5.0 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 5.0 V (selectable per bank) | — |
| Configuration Method | SRAM, in-circuit reconfigurable via external EPC or host | Serial (EPC1/EPC1064/EPC1213/EPC1441) or parallel EPROM |
| Boîtier | 84-pin J-Lead PLCC (84-LCC, J-Lead) | 84-Pin PLCC (J-Lead) |
| Type de montage | Surface Mount (J-Lead, also socketable) | Surface Mount / Socket |
| Speed Grade | -3 (fastest) | -4 |
| Température de fonctionnement | [DATA_NEEDED: commercial/industrial grade] | 0 °C to +70 °C (Commercial) |
| Statut RoHS | [DATA_NEEDED: per datasheet] | Non-compliant (legacy PLCC, lead-bearing) |
| Number of Logic Cells | — | 504 |
| Number of Logic Array Blocks (LABs) | — | 63 |
| Maximum Usable Gates | — | 6,000 |
| Number of User I/O Pins | — | 68 |
| Supply Voltage (Core) | — | 5.0 V |
| I/O Voltage (84-pin PLCC) | — | 5.0 V only (3.3 V I/O NOT supported on this package) |
| Operating Current (typical) | — | 10 mA |
| Configuration Memory Type | — | Volatile SRAM (requires boot device) |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |