EPF8636ALC84-3 vs EPF8636ALC84-4 Comparação
Comparação detalhada lado a lado de EPF8636ALC84-3 por Intel e EPF8636ALC84-4 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EPF8636ALC84-3 | EPF8636ALC84-4 |
|---|---|---|
| Marca | Intel | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Última compra | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $18,75 | $24,30 |
| Family | FLEX 8000 | FLEX 8000 |
| Usable Gates | 6,000 | — |
| Logic Elements / Cells | 504 | — |
| Logic Array Blocks (LABs) | 63 | — |
| Embedded Array Blocks (EABs) | 6 (2,048 bits each, 12,288 total RAM bits) | — |
| User I/Os | 68 | — |
| Maximum Operating Frequency | 125 MHz | 125 MHz |
| Process Technology | 0.42 µm CMOS, 5-metal | 0.42 µm CMOS SRAM |
| Core Supply Voltage | 5.0 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 5.0 V (selectable per bank) | — |
| Configuration Method | SRAM, in-circuit reconfigurable via external EPC or host | Serial (EPC1/EPC1064/EPC1213/EPC1441) or parallel EPROM |
| Encapsulamento | 84-pin J-Lead PLCC (84-LCC, J-Lead) | 84-Pin PLCC (J-Lead) |
| Tipo de montagem | Surface Mount (J-Lead, also socketable) | Surface Mount / Socket |
| Speed Grade | -3 (fastest) | -4 |
| Temperatura de operação | [DATA_NEEDED: commercial/industrial grade] | 0 °C to +70 °C (Commercial) |
| Status RoHS | [DATA_NEEDED: per datasheet] | Non-compliant (legacy PLCC, lead-bearing) |
| Number of Logic Cells | — | 504 |
| Number of Logic Array Blocks (LABs) | — | 63 |
| Maximum Usable Gates | — | 6,000 |
| Number of User I/O Pins | — | 68 |
| Supply Voltage (Core) | — | 5.0 V |
| I/O Voltage (84-pin PLCC) | — | 5.0 V only (3.3 V I/O NOT supported on this package) |
| Operating Current (typical) | — | 10 mA |
| Configuration Memory Type | — | Volatile SRAM (requires boot device) |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |