EPF8820ARC208-3-NW vs EPF8820ARC208-2A Comparaison
Comparaison détaillée côte à côte de EPF8820ARC208-3-NW par Altera et EPF8820ARC208-2A par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPF8820ARC208-2A - FLEX 8000 FPGA, 672 Logic Elements, 152 I/O | Altera
EPF8820ARC208-2A ObsoleteComparaison des spécifications
| Paramètre | EPF8820ARC208-3-NW | EPF8820ARC208-2A |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $110,00 | $14,10 |
| Family | FLEX 8000 | FLEX 8000 |
| Usable Gates | 8,000 | — |
| Logic Elements (LEs) | 672 | — |
| Registers | 1,500 | — |
| User I/O Pins | 152 | 152 |
| Tension d'alimentation | 4.75 V to 5.25 V | — |
| Process Technology | CMOS, SRAM-based | CMOS SRAM |
| Boîtier | 208-BFQFP / 208-RQFP (28x28 mm) Exposed Pad | 208-pin S-PQFP (Shrink Plastic Quad Flat Pack) with exposed pad |
| Type de montage | Surface Mount | Surface Mount |
| Configuration Method | SRAM, requires external configuration device | Serial SRAM, EPC1/EPC1064/EPC1213/EPC1441 PROM, or controller |
| In-Circuit Reconfigurability (ICR) | Yes | — |
| JTAG / Boundary Scan | Yes | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | 0 °C to 70 °C (commercial) |
| Packaging | Tray | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: check distributor listing] |
| Device Type | — | FPGA (Field Programmable Gate Array) |
| Logic Elements | — | 672 |
| Logic Array Blocks (LABs) | — | 84 |
| Embedded Array Blocks (EABs) | — | [DATA_NEEDED: EAB count] |
| Dedicated Inputs | — | 4 |
| Total RAM Bits | — | [DATA_NEEDED: distributed RAM bits] |
| Supply Voltage (VCCINT) | — | 4.75 V to 5.25 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V or 5.0 V selectable |
| Propagation Delay (tPD) | — | 5 ns (typical, -2A speed grade) |
| Terminal Pitch | — | 0.500 mm |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |