EPM1270T144C5N vs EPM570T144C5N Comparaison
Comparaison détaillée côte à côte de EPM1270T144C5N par Altera et EPM570T144C5N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM1270T144C5N - MAX II CPLD, 980 LEs, 212 I/O, TQFP-144 | Intel/Altera
EPM1270T144C5N ✓ ActifComparaison des spécifications
| Paramètre | EPM1270T144C5N | EPM570T144C5N |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $19,75 | $9,35 |
| Family | MAX II | MAX II |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 980 | — |
| Logic Elements (LEs) | 1270 | 570 |
| Maximum User I/Os | 212 | — |
| Number of Logic Array Blocks (LABs) | 127 | — |
| Process Technology | 0.18 µm | 0.18 µm 6-layer-metal flash |
| Propagation Delay (tPD) | 6.2 ns | 5.5 ns (typical, [DATA_NEEDED: exact speed grade]) |
| Maximum Internal Frequency | 201.1 MHz | — |
| Supply Voltage (Core) | 2.5 V / 3.3 V | — |
| Supply Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Boîtier | TQFP-144 (T144), 22 x 22 mm, 0.5 mm pitch | TQFP-144 (20 × 20 mm, 0.5 mm pitch) |
| Température de fonctionnement | 0 °C to +85 °C (Commercial) | 0 °C to +85 °C (commercial, C5 grade) |
| Speed Grade | -5 | — |
| Programming Interface | JTAG (IEEE 1149.1), In-System Programmable | IEEE 1149.1 JTAG (in-system programmable) |
| Configuration Memory | Internal flash (non-volatile, instant-on) | — |
| Statut RoHS | Compliant (lead-free) | Compliant |
| Sans halogène | Compliant | — |
| Type de montage | Surface Mount | Surface Mount |
| Series | — | MAX II Device |
| Macrocells | — | 440 |
| User I/Os | — | 116 |
| Internal User Flash Memory | — | 8 Kbit |
| Global Clocks | — | 4 |
| Core Voltage (VCCINT) | — | 1.8 V (typical, internally regulated) |
| I/O Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (multi-voltage, per bank) |
| Maximum User I/O Pins | — | 116 |
| Maximum Frequency (fMAX) | — | 201.1 MHz |
| Configuration Storage | — | On-chip non-volatile flash |
| Supported I/O Standards | — | LVCMOS, LVTTL, PCI, LVDS, SSTL (per bank VCCIO) |
| Lead-Free | — | Yes |
| Niveau MSL | — | 3 (per JEDEC J-STD-020) |
| Design Software | — | Intel Quartus II (MAX II device support) |