EPM3032ATI44-10N vs EPM3032ALC44-10N Comparaison
Comparaison détaillée côte à côte de EPM3032ATI44-10N par Intel et EPM3032ALC44-10N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM3032ATI44-10N | EPM3032ALC44-10N |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $5,10 | $0,94 |
| Family | MAX 3000A | MAX 3000A |
| Logic Capacity | 600 usable gates | — |
| Number of Macrocells | 32 | — |
| Number of User I/Os | 34 | — |
| Boîtier / Format | TQFP-44 (10x10 mm, 0.8 mm pitch) | — |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V typical) | 3.3 V |
| MultiVolt I/O Interface | 5.0 V, 3.3 V, 2.5 V compatible | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Counter Frequency (fCNT) | 103.1 MHz | — |
| Setup Time (tSU) | [DATA_NEEDED: setup time] | — |
| Programmability | In-System Programmable (ISP) via IEEE Std. 1149.1 JTAG | — |
| ISP Standard | IEEE Std. 1532 compliant | — |
| Configuration Memory | Non-volatile EEPROM | — |
| Hot-Socketing Support | Yes | — |
| Température de fonctionnement | -40C to +85C (industrial, 'I' grade) | [DATA_NEEDED: industrial/commercial range] |
| Type de montage | Surface Mount | Surface Mount |
| Statut RoHS | RoHS Non-Compliant (contains lead) | [DATA_NEEDED: compliant or non-compliant] |
| Lead-Free Status | Contains lead | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Gates | — | 600 gates |
| Macrocells | — | 32 |
| Logic Array Blocks (LABs) | — | 2 |
| User I/O Pins | — | 34 |
| Propagation Delay (tPD) | — | 10 ns |
| Internal fMAX | — | 103.1 MHz |
| I/O Voltage (VCCIO) | — | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O) |
| Technology | — | CMOS EEPROM-based |
| In-System Programmability | — | Yes, via IEEE 1149.1 JTAG |
| ISP Standard Compliance | — | IEEE Std. 1532 |
| Boundary-Scan Test (BST) | — | Yes, IEEE 1149.1 compliant |
| Boîtier | — | 44-pin PLCC (J-Lead, surface mount) |