EPM3032ATI44-10N vs EPM3032ALC44-10N 对比

详细并排对比 EPM3032ATI44-10N 出自 Intel 和 EPM3032ALC44-10N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3032ATI44-10N EPM3032ALC44-10N
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $5.10 $0.94
Family MAX 3000A MAX 3000A
Logic Capacity 600 usable gates —
Number of Macrocells 32 —
Number of User I/Os 34 —
封装 / 外壳 TQFP-44 (10x10 mm, 0.8 mm pitch) —
Supply Voltage (VCCINT) 3.0 V to 3.6 V (3.3 V typical) 3.3 V
MultiVolt I/O Interface 5.0 V, 3.3 V, 2.5 V compatible —
Pin-to-Pin Delay (tPD) 10 ns —
Counter Frequency (fCNT) 103.1 MHz —
Setup Time (tSU) [DATA_NEEDED: setup time] —
Programmability In-System Programmable (ISP) via IEEE Std. 1149.1 JTAG —
ISP Standard IEEE Std. 1532 compliant —
Configuration Memory Non-volatile EEPROM —
Hot-Socketing Support Yes —
工作温度 -40C to +85C (industrial, 'I' grade) [DATA_NEEDED: industrial/commercial range]
安装类型 Surface Mount Surface Mount
RoHS 状态 RoHS Non-Compliant (contains lead) [DATA_NEEDED: compliant or non-compliant]
Lead-Free Status Contains lead —
Product Type — CPLD (Complex Programmable Logic Device)
Logic Gates — 600 gates
Macrocells — 32
Logic Array Blocks (LABs) — 2
User I/O Pins — 34
Propagation Delay (tPD) — 10 ns
Internal fMAX — 103.1 MHz
I/O Voltage (VCCIO) — 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O)
Technology — CMOS EEPROM-based
In-System Programmability — Yes, via IEEE 1149.1 JTAG
ISP Standard Compliance — IEEE Std. 1532
Boundary-Scan Test (BST) — Yes, IEEE 1149.1 compliant
封装 — 44-pin PLCC (J-Lead, surface mount)

数据手册与资源

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