EPM3064ATI44-10N vs EPM3064AT100-10N Comparaison
Comparaison détaillée côte à côte de EPM3064ATI44-10N par Altera et EPM3064AT100-10N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM3064ATI44-10N | EPM3064AT100-10N |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $3,95 | $5,45 |
| Family | MAX 3000A | MAX 3000A |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 64 | 64 |
| Usable Gates | 1250 | 1,250 |
| User I/Os | 34 | — |
| Dedicated Inputs | 4 | — |
| Logic Blocks | 4 | — |
| Pin-to-Pin Delay | 10 ns (-10 speed grade) | — |
| Maximum Frequency (fMAX) | 100 MHz | — |
| Programmable Type | In-System Programmable (EEPROM) | — |
| ISP Interface | IEEE Std. 1149.1 (JTAG) | — |
| ISP Standard Compliance | IEEE Std. 1532 | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 2.5 V (MultiVolt) | — |
| Température de fonctionnement | -40C to +85C (Industrial, "N" suffix) | — |
| Boîtier | 44-pin TQFP | TQFP-100 (T100), 14 mm x 14 mm |
| Process Technology | CMOS EEPROM | — |
| Boundary-Scan Test | Built-in (JTAG) | — |
| Type de montage | Surface Mount | — |
| Lead-Free Status | Contains Lead (per digchip datasheet excerpt) | — |
| Statut RoHS | Non-Compliant (per digchip datasheet excerpt) | [DATA_NEEDED: RoHS compliance status] |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 4 |
| User I/O Pins | — | 66 |
| Speed Grade | — | -10 (10 ns pin-to-pin delay) |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Bank Voltage | — | 3.3 V |
| 5 V Tolerant Inputs | — | Yes (via clamping diodes) |
| Configuration Memory | — | EEPROM (non-volatile) |
| Programming Interface | — | JTAG (IEEE Std. 1149.1) with pin-locking |
| ISP Compliance | — | IEEE Std. 1532 |
| Boundary-Scan Test (BST) | — | IEEE Std. 1149.1 compliant |
| Operating Temperature (Commercial) | — | 0C to +70C |
| Lead-Free | — | [DATA_NEEDED: lead-free finish] |