EPM3064ATI44-10N vs EPM3064AT100-10N Comparison

Detailed side-by-side comparison of EPM3064ATI44-10N by Altera and EPM3064AT100-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3064ATI44-10N EPM3064AT100-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $3.95 $5.45
Family MAX 3000A MAX 3000A
Product Type CPLD (Complex Programmable Logic Device) β€”
Macrocells 64 64
Usable Gates 1250 1,250
User I/Os 34 β€”
Dedicated Inputs 4 β€”
Logic Blocks 4 β€”
Pin-to-Pin Delay 10 ns (-10 speed grade) β€”
Maximum Frequency (fMAX) 100 MHz β€”
Programmable Type In-System Programmable (EEPROM) β€”
ISP Interface IEEE Std. 1149.1 (JTAG) β€”
ISP Standard Compliance IEEE Std. 1532 β€”
Core Supply Voltage (VCCINT) 3.3 V β€”
I/O Supply Voltage (VCCIO) 3.3 V or 2.5 V (MultiVolt) β€”
Operating Temperature -40C to +85C (Industrial, "N" suffix) β€”
Package 44-pin TQFP TQFP-100 (T100), 14 mm x 14 mm
Process Technology CMOS EEPROM β€”
Boundary-Scan Test Built-in (JTAG) β€”
Mounting Type Surface Mount β€”
Lead-Free Status Contains Lead (per digchip datasheet excerpt) β€”
RoHS Status Non-Compliant (per digchip datasheet excerpt) [DATA_NEEDED: RoHS compliance status]
Device Type β€” CPLD (Complex Programmable Logic Device)
Logic Array Blocks (LABs) β€” 4
User I/O Pins β€” 66
Speed Grade β€” -10 (10 ns pin-to-pin delay)
Supply Voltage (VCCINT) β€” 3.3 V
I/O Bank Voltage β€” 3.3 V
5 V Tolerant Inputs β€” Yes (via clamping diodes)
Configuration Memory β€” EEPROM (non-volatile)
Programming Interface β€” JTAG (IEEE Std. 1149.1) with pin-locking
ISP Compliance β€” IEEE Std. 1532
Boundary-Scan Test (BST) β€” IEEE Std. 1149.1 compliant
Operating Temperature (Commercial) β€” 0C to +70C
Lead-Free β€” [DATA_NEEDED: lead-free finish]

Datasheets & Resources

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