EPM3256AQC208-10N vs EPM3512AQC208-10-10N Comparaison
Comparaison détaillée côte à côte de EPM3256AQC208-10N par Altera et EPM3512AQC208-10-10N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM3512AQC208-10-10N - MAX 3000A CPLD 512 Macrocells 208-PQFP | Altera
EPM3512AQC208-10-10N ObsoleteComparaison des spécifications
| Paramètre | EPM3256AQC208-10N | EPM3512AQC208-10-10N |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $4,62 | $31,20 |
| Series | MAX 3000A | — |
| Programmable Type | In-System Programmable (EEPROM) | — |
| Number of Macrocells | 256 | — |
| Number of Logic Elements/Blocks | 16 LABs | — |
| Usable Gates | 10,000 | 10,000 |
| Number of I/O Pins | 161 (158 user I/O per Arrow listing) | — |
| Propagation Delay (tpd) | 10 ns (max) | — |
| Maximum Counter Frequency | 227.3 MHz | — |
| Supply Voltage - Internal | 3.0 V to 3.6 V (3.3 V typical) | — |
| Température de fonctionnement | 0C to +70C (Commercial) | 0 °C to +70 °C (commercial) |
| Boîtier / Format | 208-BFQFP / 208-PQFP (28x28 mm) | — |
| Type de montage | Surface Mount | Surface Mount |
| ISP Compliance | IEEE Std. 1532 | — |
| Boundary Scan | IEEE Std. 1149.1 (JTAG) | — |
| I/O Tolerance | 5 V tolerant, MultiVolt interface | — |
| Statut RoHS | [DATA_NEEDED: lead-free status - non-RoHS suffix 'N' typically indicates lead-free finish, but datasheet not present in data] | — |
| Family | — | MAX 3000A |
| Macrocells | — | 512 |
| User I/Os | — | 172 |
| Logic Elements / LABs | — | 16 Logic Array Blocks |
| Propagation Delay (tPD) | — | 10 ns (-10 speed grade) |
| Maximum Frequency (fCNT) | — | 87 MHz |
| Supply Voltage - Core (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 2.5 V / 3.3 V / 5.0 V |
| Process Technology | — | CMOS EEPROM |
| In-System Programmability | — | Yes, IEEE Std. 1532 compliant |
| Boundary-Scan (JTAG) | — | Yes, IEEE 1149.1 |
| PCI-SIG Compliance | — | PCI Local Bus Specification Rev 2.2 (at -10 speed grade) |
| Boîtier | — | 208-pin PQFP (Plastic Quad Flat Pack) |
| Lead-Free / RoHS | — | [DATA_NEEDED: RoHS status] |