Altera

EPM3256AQC208-10N - 256-Macro MAX 3000A 3.3V CPLD | Altera

Référence : EPM3256AQC208-10N ✗ Fin de vie

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3.0 V to 3.6 V (3.3 V typical) Vdss 208-BFQFP / 208-PQFP (28x28 mm) Package 227.3 MHz Speed

À partir de $4.62 USD / unité

MOQ : 1 |

Prix mis à jour : 2026-09-12

Tarifs dégressifs

Qté	Prix unitaire	Total
1	$7.17	$7,17
10	$6.45	$64,50
100	$5.74	$574,00
500	$5.1	$2 550,00
1 000	$4.62	$4 620,00

ℹ️ Tous les prix sont en USD

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EPM3256AQC208-10N Présentation

The Altera EPM3256AQC208-10N is a high-density, EEPROM-based Complex Programmable Logic Device (CPLD) from the legacy MAX 3000A family, housed in a 208-pin PQFP package and rated for the commercial 0C to 70C operating range. The device delivers 256 macrocells, up to 10,000 usable gates, 161 user I/Os, and a 10 ns pin-to-pin propagation delay (tpd) in the -10 speed grade. Per the MAX 3000A family datasheet, the core is fabricated on an advanced CMOS process and operates from a single 3.3 V supply while remaining 5 V-tolerant on its I/O pins.

What is a CPLD? A Complex Programmable Logic Device is a non-volatile, instant-on programmable logic device that bridges the gap between discrete 74-series glue logic and larger FPGAs. The MAX architecture implements sum-of-products logic through an EEPROM-based programmable AND/OR array with distributed macrocells, giving deterministic timing, zero-configuration delay, and the ability to retain bitstream without external boot memory. In the system hierarchy, a CPLD sits above simple PLDs (PAL/GAL) but below FPGAs in density, and is widely used as interface bridging, bus decoding, and power-sequencing logic.

Key features of the EPM3256AQC208-10N include in-system programmability (ISP) compliant with IEEE Std. 1532, JTAG-based boundary-scan test support via IEEE 1149.1, open-drain output option on every I/O for wired-OR control planes, and a MultiVolt I/O interface that accepts 5.0 V, 3.3 V, and 2.5 V signaling on a single device. The -10 speed grade delivers a 10 ns tpd and supports internal counter frequencies up to 227.3 MHz, sufficient for state-machine and address-decoding tasks.

Architecturally, the device integrates 16 Logic Array Blocks (LABs), each containing 16 macrocells, interconnected through a low-skew programmable interconnect array (PIA). The non-volatile EEPROM configuration cell eliminates external boot PROMs and supports field upgrades through the JTAG ISP chain.

Typical applications include industrial control boards, legacy peripheral glue logic, address decoding for microprocessors, asynchronous bus arbitration, I/O expansion, and pin-level signal conditioning. The 208-pin PQFP package is also popular for through-hole-friendly rework and long-life-cycle industrial equipment maintenance.

When designing with this part, note that the 208-pin PQFP (28x28 mm body, 0.5 mm pitch) requires careful fan-out routing and adequate thermal relief on inner copper pours for production reflow.

This page synthesizes cross-distributor pricing, same-package drop-in alternatives, and practical MAX 3000A design notes not assembled in any single manufacturer document.

Alternatives de remplacement direct pour EPM3256AQC208-10N — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.

Variantes de cette série

Modèles de la même série directement compatibles avec EPM3256AQC208-10N (même facteur de forme et même empreinte) — différant par Operating Temperature, Package, Usable Gates, Propagation Delay (tPD), Maximum Frequency (fCNT).

EPM3256AFC256-10N

Altera

Operating Temperature: 0 C to 70 C (commercial)

Package: 256-pin FineLine BGA

Usable Gates: 5,000 gates