EPM3256ATI144-7N vs EPM3256ATC144-10 Comparaison
Comparaison détaillée côte à côte de EPM3256ATI144-7N par Altera et EPM3256ATC144-10 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM3256ATI144-7N - 256-Macrocell MAX 3000A CPLD, 7.5ns, TQFP-144 | Altera
EPM3256ATI144-7N ObsoleteIntel
EPM3256ATC144-10 - 256-Macrocell CPLD, 10ns, 144-TQFP | Intel / Altera
EPM3256ATC144-10 ObsoleteComparaison des spécifications
| Paramètre | EPM3256ATI144-7N | EPM3256ATC144-10 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $10,95 | $9,75 |
| Family | MAX 3000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macrocells | 256 | 256 |
| Usable Gates | 5,000 | 5,000 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Maximum User I/O Pins | 116 | — |
| Propagation Delay (tPD) | 7.5 ns (typical) | — |
| Maximum Internal Frequency | 126.6 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V | 3.0 V to 3.6 V (3.3 V nominal) |
| I/O Supply Voltage (VCCIO) | 3.3 V or 2.5 V | — |
| MultiVolt I/O Logic Levels | 5.0 V / 3.3 V / 2.5 V | — |
| Programming Technology | EEPROM (in-system programmable) | — |
| JTAG / ISP | IEEE Std. 1532 compliant | — |
| Boundary Scan | IEEE Std. 1149.1 (JTAG) | — |
| Hot-Socketing Support | Yes | — |
| Boîtier | TQFP-144 (20 x 20 mm, 0.5 mm pitch) | 144-pin TQFP (20x20 mm) |
| Température de fonctionnement | -40C to +85C (industrial) | 0 C to +70 C (Commercial) |
| Statut RoHS | Compliant (lead-free) | Non-compliant (original EPM3256ATC144-10); N suffix variant is lead-free |
| Manufacturer | — | Intel (formerly Altera) |
| Series | — | MAX 3000A |
| Programmable Type | — | In-System Programmable (EEPROM-based, IEEE 1532) |
| Number of I/O Pins | — | 116 |
| Propagation Delay (tpd max) | — | 10 ns |
| Counter Frequency (max) | — | 95.2 MHz |
| I/O Logic Level Support | — | MultiVolt - 5.0 V, 3.3 V, 2.5 V |
| Type de montage | — | Surface Mount |
| JTAG / Boundary Scan | — | Yes (IEEE 1149.1) |
| Process Technology | — | CMOS EEPROM |