EPM3256ATI144-7N vs EPM3256ATC144-10 对比
详细并排对比 EPM3256ATI144-7N 出自 Altera 和 EPM3256ATC144-10 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
EPM3256ATI144-7N - 256-Macrocell MAX 3000A CPLD, 7.5ns, TQFP-144 | Altera
EPM3256ATI144-7N ObsoleteIntel
EPM3256ATC144-10 - 256-Macrocell CPLD, 10ns, 144-TQFP | Intel / Altera
EPM3256ATC144-10 Obsolete规格对比
| 参数 | EPM3256ATI144-7N | EPM3256ATC144-10 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $10.95 | $9.75 |
| Family | MAX 3000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macrocells | 256 | 256 |
| Usable Gates | 5,000 | 5,000 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Maximum User I/O Pins | 116 | — |
| Propagation Delay (tPD) | 7.5 ns (typical) | — |
| Maximum Internal Frequency | 126.6 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V | 3.0 V to 3.6 V (3.3 V nominal) |
| I/O Supply Voltage (VCCIO) | 3.3 V or 2.5 V | — |
| MultiVolt I/O Logic Levels | 5.0 V / 3.3 V / 2.5 V | — |
| Programming Technology | EEPROM (in-system programmable) | — |
| JTAG / ISP | IEEE Std. 1532 compliant | — |
| Boundary Scan | IEEE Std. 1149.1 (JTAG) | — |
| Hot-Socketing Support | Yes | — |
| 封装 | TQFP-144 (20 x 20 mm, 0.5 mm pitch) | 144-pin TQFP (20x20 mm) |
| 工作温度 | -40C to +85C (industrial) | 0 C to +70 C (Commercial) |
| RoHS 状态 | Compliant (lead-free) | Non-compliant (original EPM3256ATC144-10); N suffix variant is lead-free |
| Manufacturer | — | Intel (formerly Altera) |
| Series | — | MAX 3000A |
| Programmable Type | — | In-System Programmable (EEPROM-based, IEEE 1532) |
| Number of I/O Pins | — | 116 |
| Propagation Delay (tpd max) | — | 10 ns |
| Counter Frequency (max) | — | 95.2 MHz |
| I/O Logic Level Support | — | MultiVolt - 5.0 V, 3.3 V, 2.5 V |
| 安装类型 | — | Surface Mount |
| JTAG / Boundary Scan | — | Yes (IEEE 1149.1) |
| Process Technology | — | CMOS EEPROM |