EPM3512AQC208-10-10N vs EPM3512AQC208-10S Comparaison
Comparaison détaillée côte à côte de EPM3512AQC208-10-10N par Altera et EPM3512AQC208-10S par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM3512AQC208-10-10N - MAX 3000A CPLD 512 Macrocells 208-PQFP | Altera
EPM3512AQC208-10-10N Obsolete
Comparaison des spécifications
| Paramètre | EPM3512AQC208-10-10N | EPM3512AQC208-10S |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $31,20 | $9,75 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | 1750 |
| User I/Os | 172 | 208 |
| Logic Elements / LABs | 16 Logic Array Blocks | — |
| Propagation Delay (tPD) | 10 ns (-10 speed grade) | — |
| Maximum Frequency (fCNT) | 87 MHz | — |
| Supply Voltage - Core (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V | — |
| Process Technology | CMOS EEPROM | EEPROM-based CMOS |
| In-System Programmability | Yes, IEEE Std. 1532 compliant | — |
| Boundary-Scan (JTAG) | Yes, IEEE 1149.1 | Yes (1149.1 compliant) |
| PCI-SIG Compliance | PCI Local Bus Specification Rev 2.2 (at -10 speed grade) | — |
| Température de fonctionnement | 0 °C to +70 °C (commercial) | 0C to +70C (commercial) |
| Boîtier | 208-pin PQFP (Plastic Quad Flat Pack) | 208-pin FineLine BGA-256 |
| Type de montage | Surface Mount | — |
| Lead-Free / RoHS | [DATA_NEEDED: RoHS status] | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 32 (16 macrocells each) |
| Speed Grade | — | -10 (tPD1 = 7.5 ns) |
| Propagation Delay (tPD1) | — | 7.5 ns (pin-to-pin) |
| Supply Voltage - VCCINT (internal) | — | 3.3 V |
| Supply Voltage - VCCIO (I/O) | — | 2.5 V, 3.3 V, or 5.0 V (MultiVolt) |
| Programming Technology | — | CMOS EEPROM |
| In-System Programmability (ISP) | — | Yes (IEEE Std. 1149.1 JTAG) |
| PCI Compliance | — | Yes (PCI Local Bus Specification Rev 2.2) |
| Program/Erase Endurance | — | 100 cycles minimum |
| Logic Family | — | CMOS |
| Statut RoHS | — | [DATA_NEEDED: rohs_status] |