EPM3512AQC208-3 vs EPM3512AQC208-10N Comparaison
Comparaison détaillée côte à côte de EPM3512AQC208-3 par Altera et EPM3512AQC208-10N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM3512AQC208-3 - MAX 3000A CPLD, 512 Macrocells, 172 I/O, PQFP-208 | Altera
EPM3512AQC208-3 ⚠ Dernier achatComparaison des spécifications
| Paramètre | EPM3512AQC208-3 | EPM3512AQC208-10N |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $27,80 | $42,80 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 16 (32 macrocells each) | 16 |
| Maximum User I/O Pins | 172 | — |
| Boîtier | PQFP-208 | 208-pin PQFP (Plastic Quad Flat Pack) |
| Speed Grade | -3 | -10 |
| Supply Voltage - Core (VCCINT) | 3.3 V | — |
| I/O Bank Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (multiVolt) | — |
| In-System Programmability | Yes (IEEE Std. 1532 compliant) | — |
| Boundary-Scan Test | Yes (IEEE Std. 1149.1 / JTAG) | — |
| Program/Erase Cycles | 100 minimum [DATA_NEEDED: exact datasheet figure] | — |
| Non-Volatile Configuration | Yes (EEPROM-based) | — |
| Température de fonctionnement | [DATA_NEEDED: industrial/commercial grade range] | 0 C to 70 C (commercial) |
| Statut RoHS | [DATA_NEEDED: confirm from datasheet] | [DATA_NEEDED: RoHS status not in verified web data] |
| Type de montage | Surface Mount | — |
| Niveau MSL | [DATA_NEEDED: moisture sensitivity level] | — |
| Usable Gates | — | Up to 10,000 |
| User I/Os | — | 172 |
| Tension d'alimentation | — | 3.3 V |
| Pin-to-Pin Delay | — | 4.5 ns (-10 speed grade) |
| Maximum Internal Frequency | — | 227.3 MHz |
| Process Technology | — | CMOS EEPROM |
| In-System Programming | — | IEEE Std. 1149.1 JTAG, IEEE Std. 1532 |
| Boundary-Scan Test (BST) | — | Built-in, IEEE 1149.1 compliant |
| I/O Standards | — | MultiVolt (1.8V / 2.5V / 3.3V) |