EPM3512ATC144 vs EPM3256ATC144-10N Comparaison
Comparaison détaillée côte à côte de EPM3512ATC144 par Altera et EPM3256ATC144-10N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM3256ATC144-10N - 256-Macro CPLD, 10ns, 144-TQFP | Altera
EPM3256ATC144-10N ⚠ Dernier achatComparaison des spécifications
| Paramètre | EPM3512ATC144 | EPM3256ATC144-10N |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $8,75 | $14,50 |
| Family | MAX 3000A | — |
| Macrocells | 512 | — |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum User I/O Pins | 212 | — |
| Boîtier | TQFP-144 (20x20 mm) | 144-LQFP (TQFP, ATC suffix) |
| Core Supply Voltage | 3.3 V | — |
| Programming Technology | EEPROM (in-system programmable) | — |
| JTAG Interface | IEEE Std. 1149.1 (4-pin) | — |
| Maximum Frequency | 116 MHz | — |
| Propagation Delay (tPD) | [DATA_NEEDED: tPD in ns] | 10 ns |
| Product Terms per Macrocell | 32 (expandable) | — |
| I/O Standards | LVTTL, LVCMOS, 2.5 V/3.3 V/5 V tolerant | — |
| Température de fonctionnement | 0C to +70C (commercial) | 0C to +70C (commercial) [DATA_NEEDED: exact operating-temp grade letter for -10N suffix] |
| Type de montage | Surface Mount | Surface Mount |
| Niveau MSL | 3 | — |
| Statut RoHS | Compliant (lead-free suffix variants available) | [DATA_NEEDED: RoHS compliance - not explicitly confirmed in verified data] |
| Series | — | MAX 3000A |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 256 |
| Usable Gates | — | 5,000 (up to 10,000 usable in family) |
| Number of I/Os | — | 116 |
| Number of Logic Elements / Blocks | — | 16 LABs |
| Supply Voltage (VCCINT) | — | 3.3 V |
| Maximum Counter Frequency | — | 227.3 MHz |
| Global Clocks | — | 3 |
| Global Clear / OE | — | Yes (1 global clear, 1 global OE) |
| Program Memory Type | — | EEPROM (non-volatile, in-system programmable) |
| JTAG Support | — | IEEE Std. 1149.1 with pin-locking |
| ISP Compliance | — | IEEE Std. 1532 |
| Boundary-Scan Test (BST) | — | Built-in, IEEE 1149.1 compliant |
| Lead-Free / Halogen-Free | — | [DATA_NEEDED: not explicitly confirmed in verified data] |