EPM3512ATC144 vs EPM3256ATC144-10N 对比

详细并排对比 EPM3512ATC144 出自 Altera 和 EPM3256ATC144-10N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM3256ATC144-10N EPM3256ATC144-10N - 256-Macro CPLD, 10ns, 144-TQFP | Altera

EPM3256ATC144-10N - 256-Macro CPLD, 10ns, 144-TQFP | Altera

EPM3256ATC144-10N ⚠ 最后一次采购

规格对比

参数 EPM3512ATC144 EPM3256ATC144-10N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 最后采购期
库存状态 有库存 有库存
单价(USD) $8.75 $14.50
Family MAX 3000A —
Macrocells 512 —
Logic Array Blocks (LABs) 16 —
Maximum User I/O Pins 212 —
封装 TQFP-144 (20x20 mm) 144-LQFP (TQFP, ATC suffix)
Core Supply Voltage 3.3 V —
Programming Technology EEPROM (in-system programmable) —
JTAG Interface IEEE Std. 1149.1 (4-pin) —
Maximum Frequency 116 MHz —
Propagation Delay (tPD) [DATA_NEEDED: tPD in ns] 10 ns
Product Terms per Macrocell 32 (expandable) —
I/O Standards LVTTL, LVCMOS, 2.5 V/3.3 V/5 V tolerant —
工作温度 0C to +70C (commercial) 0C to +70C (commercial) [DATA_NEEDED: exact operating-temp grade letter for -10N suffix]
安装类型 Surface Mount Surface Mount
MSL 等级 3 —
RoHS 状态 Compliant (lead-free suffix variants available) [DATA_NEEDED: RoHS compliance - not explicitly confirmed in verified data]
Series — MAX 3000A
Device Type — CPLD (Complex Programmable Logic Device)
Macro Cells — 256
Usable Gates — 5,000 (up to 10,000 usable in family)
Number of I/Os — 116
Number of Logic Elements / Blocks — 16 LABs
Supply Voltage (VCCINT) — 3.3 V
Maximum Counter Frequency — 227.3 MHz
Global Clocks — 3
Global Clear / OE — Yes (1 global clear, 1 global OE)
Program Memory Type — EEPROM (non-volatile, in-system programmable)
JTAG Support — IEEE Std. 1149.1 with pin-locking
ISP Compliance — IEEE Std. 1532
Boundary-Scan Test (BST) — Built-in, IEEE 1149.1 compliant
Lead-Free / Halogen-Free — [DATA_NEEDED: not explicitly confirmed in verified data]

数据手册与资源

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