EPM5032DC-2 vs EPM5032DC20 Comparaison
Comparaison détaillée côte à côte de EPM5032DC-2 par Altera et EPM5032DC20 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5032DC-2 | EPM5032DC20 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $8,75 | $8,20 |
| Product Type | CPLD (Complex Programmable Logic Device) | UV-erasable PLD (CPLD class) |
| Series | MAX 5000 | — |
| Macrocells | 32 | 32 |
| Usable Gates (typical) | 600 | — |
| Logic Array Blocks (LABs) | 4 | — |
| Boîtier | 20-pin CDIP (Ceramic DIP) | 20-pin Ceramic DIP (DC) with UV window |
| Speed Grade | -2 (tPD ~25 ns, commercial) | — |
| Configuration Memory | EPROM (one-time programmable per generation; UV-erasable variants exist) | — |
| Supply Voltage (VCC) | 5 V (single supply, +/-5%) | 5 V (4.75 V to 5.25 V) |
| Température de fonctionnement | 0C to +70C (commercial grade) | [DATA_NEEDED: operating temperature range] |
| Programmable Pins / I/O | 20 pins (JEDEC-standard 0.300" ceramic DIP) | — |
| Programming Interface | Altera ByteBlaster / parallel-port JTAG-style ISP | — |
| Interconnect | Programmable Interconnect Array (PIA) with deterministic timing | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance - CDIP package typically pre-RoHS] | [DATA_NEEDED: RoHS compliance] |
| Type de montage | Through-Hole (DIP) | Through-Hole (DIP) |
| Niveau MSL | Not applicable (through-hole hermetic ceramic) | — |
| Device Family | — | MAX 5000 |
| Usable Gates | — | 600 |
| Propagation Delay (tPD) | — | 20 ns |
| Maximum Frequency (Fmax) | — | 71.4 MHz |
| Dedicated Inputs | — | 7 |
| I/O Pins | — | 16 (bidirectional) |
| Total Inputs (max) | — | 24 |
| Output Macrocells | — | 16 |
| Clock Inputs | — | 1 (global) |
| Architecture | — | PAL-type with Programmable Interconnect Array (PIA) |
| Process Technology | — | CMOS |