EPM5032DC-2 vs EPM5128GC Comparaison
Comparaison détaillée côte à côte de EPM5032DC-2 par Altera et EPM5128GC par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5032DC-2 | EPM5128GC |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $8,75 | $19,20 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Series | MAX 5000 | — |
| Macrocells | 32 | 128 |
| Usable Gates (typical) | 600 | — |
| Logic Array Blocks (LABs) | 4 | — |
| Boîtier | 20-pin CDIP (Ceramic DIP) | — |
| Speed Grade | -2 (tPD ~25 ns, commercial) | — |
| Configuration Memory | EPROM (one-time programmable per generation; UV-erasable variants exist) | Non-volatile UV-EPROM (windowed ceramic) |
| Supply Voltage (VCC) | 5 V (single supply, +/-5%) | — |
| Température de fonctionnement | 0C to +70C (commercial grade) | — |
| Programmable Pins / I/O | 20 pins (JEDEC-standard 0.300" ceramic DIP) | — |
| Programming Interface | Altera ByteBlaster / parallel-port JTAG-style ISP | — |
| Interconnect | Programmable Interconnect Array (PIA) with deterministic timing | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance - CDIP package typically pre-RoHS] | [DATA_NEEDED: RoHS compliance] |
| Type de montage | Through-Hole (DIP) | Through-Hole (PGA socket required) |
| Niveau MSL | Not applicable (through-hole hermetic ceramic) | — |
| Family | — | MAX 5000 |
| Usable Gates | — | 2,500 |
| Logic Elements / LABs | — | [DATA_NEEDED: LAB count] |
| User I/Os | — | 68 |
| Package Type | — | WPGA (Windowed Ceramic Pin Grid Array) |
| Package Code | — | WPGA |
| Number of Terminals | — | 68 |
| Terminal Form | — | PIN/PEG (through-hole PGA with alignment pegs) |
| Package Shape | — | Square |
| Temperature Grade | — | Commercial |
| Supply Voltage (Vcc) | — | 5 V |
| Process Technology | — | CMOS, UV-erasable |
| Architecture | — | EPLD, programmable AND/OR array with fixed OR plane |
| Propagation Delay (tpd) | — | [DATA_NEEDED: tpd in ns] |
| Maximum Frequency (fmax) | — | [DATA_NEEDED: fmax in MHz] |
| Programmable Security Bit | — | Yes |