EPM5064JC-2 vs EPM5064LC-1 Comparaison
Comparaison détaillée côte à côte de EPM5064JC-2 par Altera et EPM5064LC-1 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5064JC-2 | EPM5064LC-1 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $23,10 | $9,95 |
| Family | MAX 5000 | MAX 5000 |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 4 | 4 |
| Propagation Delay (tPD) | 45 ns | 40 ns |
| Maximum Clock Frequency (fMAX) | 50 MHz | — |
| Usable Gates | 1250 | 1.25K (approx.) |
| Dedicated Inputs | 7 | 7 |
| I/O Pins | 28 | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Technology | CMOS, UV-erasable EPROM | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | 4.75 V to 5.25 V |
| Programming Method | UV-erase + EPROM programmer (not ISP) | — |
| Boîtier | 28-pin CLCC (J-lead, ceramic, windowed) | 44-pin PLCC (Plastic Leaded Chip Carrier) |
| Température de fonctionnement | [DATA_NEEDED: commercial or industrial grade] | [DATA_NEEDED: operating temperature range] |
| Compliance | RoHS status unknown (ceramic/J-lead windowed part, legacy product) | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Internal Operating Frequency | — | 62.5 MHz |
| Input Lines | — | 36 |
| Output Lines | — | 28 |
| Programming Technology | — | OTP / UV-Erasable EPROM |
| Process Technology | — | CMOS |
| Statut RoHS | — | [DATA_NEEDED: RoHS compliance] |
| Programming Interface | — | JTAG (ByteBlaster-compatible) |