EPM5064JC-2 vs EPM5064LC-1 比較
詳細な並列比較: EPM5064JC-2 メーカー: Altera および EPM5064LC-1 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5064JC-2 | EPM5064LC-1 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $23.10 | $9.95 |
| Family | MAX 5000 | MAX 5000 |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 4 | 4 |
| Propagation Delay (tPD) | 45 ns | 40 ns |
| Maximum Clock Frequency (fMAX) | 50 MHz | — |
| Usable Gates | 1250 | 1.25K (approx.) |
| Dedicated Inputs | 7 | 7 |
| I/O Pins | 28 | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Technology | CMOS, UV-erasable EPROM | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | 4.75 V to 5.25 V |
| Programming Method | UV-erase + EPROM programmer (not ISP) | — |
| パッケージ | 28-pin CLCC (J-lead, ceramic, windowed) | 44-pin PLCC (Plastic Leaded Chip Carrier) |
| 動作温度 | [DATA_NEEDED: commercial or industrial grade] | [DATA_NEEDED: operating temperature range] |
| Compliance | RoHS status unknown (ceramic/J-lead windowed part, legacy product) | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Internal Operating Frequency | — | 62.5 MHz |
| Input Lines | — | 36 |
| Output Lines | — | 28 |
| Programming Technology | — | OTP / UV-Erasable EPROM |
| Process Technology | — | CMOS |
| RoHS ステータス | — | [DATA_NEEDED: RoHS compliance] |
| Programming Interface | — | JTAG (ByteBlaster-compatible) |