EPM5064JC1 vs EPM5064JC-2 Comparaison
Comparaison détaillée côte à côte de EPM5064JC1 par Altera et EPM5064JC-2 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5064JC1 | EPM5064JC-2 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $1,05 | $23,10 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | CPLD / EPLD (Erasable PLD) | — |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 4 | 4 |
| Usable Gates | 1.25K | 1250 |
| Maximum Operating Frequency (fCNT) | 62.5 MHz | — |
| External Clock Input (max) | 50 MHz | — |
| I/O Pins | 28 | 28 |
| Dedicated Inputs | 7 | 7 |
| Total Inputs | 36 (28 I/O + 7 dedicated + 1 clock) | — |
| Operating Voltage (VCC) | 5 V | — |
| Program Type | EPROM (one-time programmable, UV-erasable) | — |
| Process Technology | CMOS | — |
| Boîtier | 44-pin PLCC (J-Lead) | 28-pin CLCC (J-lead, ceramic, windowed) |
| Operating Temperature (JC suffix) | 0°C to +70°C (commercial) | — |
| Supply Current (ICC) | [DATA_NEEDED: ICC maximum] | — |
| Statut RoHS | unknown | — |
| Lead-Free Status | unknown | — |
| Propagation Delay (tPD) | — | 45 ns |
| Maximum Clock Frequency (fMAX) | — | 50 MHz |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Technology | — | CMOS, UV-erasable EPROM |
| Supply Voltage (VCC) | — | 5 V (4.75 V to 5.25 V) |
| Programming Method | — | UV-erase + EPROM programmer (not ISP) |
| Température de fonctionnement | — | [DATA_NEEDED: commercial or industrial grade] |
| Compliance | — | RoHS status unknown (ceramic/J-lead windowed part, legacy product) |