EPM5064JC1 vs EPM5064JC-2 对比

详细并排对比 EPM5064JC1 出自 Altera 和 EPM5064JC-2 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5064JC1 EPM5064JC-2
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $1.05 $23.10
Family MAX 5000 MAX 5000
Device Type CPLD / EPLD (Erasable PLD) —
Macrocells 64 64
Logic Array Blocks (LABs) 4 4
Usable Gates 1.25K 1250
Maximum Operating Frequency (fCNT) 62.5 MHz —
External Clock Input (max) 50 MHz —
I/O Pins 28 28
Dedicated Inputs 7 7
Total Inputs 36 (28 I/O + 7 dedicated + 1 clock) —
Operating Voltage (VCC) 5 V —
Program Type EPROM (one-time programmable, UV-erasable) —
Process Technology CMOS —
封装 44-pin PLCC (J-Lead) 28-pin CLCC (J-lead, ceramic, windowed)
Operating Temperature (JC suffix) 0°C to +70°C (commercial) —
Supply Current (ICC) [DATA_NEEDED: ICC maximum] —
RoHS 状态 unknown —
Lead-Free Status unknown —
Propagation Delay (tPD) — 45 ns
Maximum Clock Frequency (fMAX) — 50 MHz
Interconnect — Programmable Interconnect Array (PIA)
Technology — CMOS, UV-erasable EPROM
Supply Voltage (VCC) — 5 V (4.75 V to 5.25 V)
Programming Method — UV-erase + EPROM programmer (not ISP)
工作温度 — [DATA_NEEDED: commercial or industrial grade]
Compliance — RoHS status unknown (ceramic/J-lead windowed part, legacy product)

数据手册与资源

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