EPM5128GI vs EPM5128JC-2 Comparaison
Comparaison détaillée côte à côte de EPM5128GI par Altera et EPM5128JC-2 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5128GI | EPM5128JC-2 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $19,85 | $21,75 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX 5000 | MAX 5000 |
| Logic Cells / Macrocells | 128 | — |
| Propagation Delay (tPD) | 55 ns | 45 ns (max) |
| Tension d'alimentation | 5 V | 5 V (nominal) |
| Technology | CMOS, UV-erasable EPROM | — |
| Boîtier | CPGA-68 (Ceramic Pin Grid Array, windowed) | 68-pin CQCC (Ceramic Quad Flat Pack), windowed |
| Nombre de broches | 68 | — |
| Type de montage | Through-hole (socketed PGA) | Surface Mount |
| Operating Temperature Grade | Industrial | — |
| Programmability | UV-erasable (windowed), field-programmable | — |
| Configuration Memory | Non-volatile EPROM (no external boot device) | — |
| Manufacturer | Altera Corporation (now Intel PSG) | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | Non-compliant (ceramic windowed package contains lead-bearing solder) |
| Statut du cycle de vie | Obsolete (last produced by Altera, legacy stock via distributors) | — |
| Device Type | — | UV-Erasable Programmable Logic Device (PLD) |
| Macrocells | — | 128 |
| Dedicated Inputs | — | 7 |
| Maximum Counter Frequency (fCNT) | — | 50 MHz |
| Input Setup Time (tSU) | — | 7.5 ns |
| Output Drive Current (IOH/IOL) | — | 12 mA DC |
| Process Technology | — | CMOS |
| Température de fonctionnement | — | [DATA_NEEDED: operating temperature range] |
| Program/Erase Method | — | UV (ceramic window) |
| Erase/Program Cycles | — | [DATA_NEEDED: minimum erase/program cycles] |
| Logic Family | — | TTL-compatible I/O |