EPM5128GI - 128-Cell UV PLD, MAX 5000, CPGA-68 | Altera
Référence : EPM5128GI ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $38.5 | $38,50 |
| 10 | $32.75 | $327,50 |
| 100 | $27.4 | $2 740,00 |
| 500 | $23.1 | $11 550,00 |
| 1 000 | $19.85 | $19 850,00 |
EPM5128GI Présentation
A CPLD (Complex Programmable Logic Device) is a non-volatile, factory-programmable integrated circuit that combines multiple PAL/GAL macrocell blocks with a programmable interconnect matrix, sitting in the programmable logic taxonomy between simple SPLDs/CPLDs and larger FPGAs. CPLDs are deterministic, have predictable timing (fixed propagation delay), retain configuration without external memory, and are typically used for glue logic, bus interfacing, address decoding, and state-machine implementation. The MAX 5000 family was Altera's first-generation high-density UV-erasable CPLD family, positioned for prototyping and production designs that benefit from windowed erasure and reprogramming.
Key features of the EPM5128GI include 128 macrocells, 100% factory-tested logic, 5V CMOS technology, and a ceramic windowed package that allows repeated UV erasure for prototyping iterations. The CPGA-68 ceramic package provides robust mechanical and thermal performance suitable for industrial and military-grade applications. The device is also offered in plastic OTP (one-time-programmable) variants for high-volume production where re-programmability is not required.
Architecturally, the MAX 5000 family uses Altera's classic EPLD architecture with Logic Array Blocks (LABs) and a global programmable interconnect array (PIA), which provides fully deterministic, hazard-free combinatorial and registered logic. The EPROM-based configuration cell technology ensures non-volatile storage of the user's logic design with no external boot PROM required. The 55 ns propagation delay supports interfaces up to approximately 18 MHz in combinatorial paths.
Typical applications include industrial control logic, address decoding and bus interfacing in legacy 5V systems, prototyping platforms where iterative UV erasure is required, glue logic for microprocessor and microcontroller peripherals, state-machine controllers, and military/aerospace systems that require a windowed, reprogrammable, hermetic ceramic package.
When designing with this device, account for the CPGA-68 socket requirement (it is not surface-mountable) and verify that your programmer supports the MAX 5000 family algorithm. The 5V-only supply and 55 ns speed grade place it in legacy designs; modern 3.3V systems should consider MAX 7000 or MAX II families instead.
This page synthesizes distributor pricing, datasheet links, and same-family Altera alternatives for engineers evaluating or sourcing the EPM5128GI — practical context that goes beyond the original datasheet.
Alternatives de remplacement direct pour EPM5128GI — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec EPM5128GI (même facteur de forme et même empreinte) — différant par Mounting Type, Package, Propagation Delay (tPD), Configuration Memory, Device Type.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
EPM5128GC
✅ Remplacement direct✓ En stock
$19.2 / unité
Voir la fiche technique →EPM5128GC-1
✅ Remplacement direct✓ En stock
$18.95 / unité
Voir la fiche technique →EPM5128GC-2
✅ Remplacement direct✓ En stock
$8.95 / unité
Voir la fiche technique →EPM5128GC2
✅ Remplacement direct✓ En stock
$54 / unité
Voir la fiche technique →EPM5128GI-1
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
EPM5128GI Valeurs maximales et caractéristiques électriques
| Product Type | CPLD (Complex Programmable Logic Device) |
| Family | MAX 5000 |
| Logic Cells / Macrocells | 128 |
| Propagation Delay (tPD) | 55 ns |
| Tension d'alimentation | 5 V |
| Technology | CMOS, UV-erasable EPROM |
| Boîtier | CPGA-68 (Ceramic Pin Grid Array, windowed) |
| Nombre de broches | 68 |
| Type de montage | Through-hole (socketed PGA) |
| Operating Temperature Grade | Industrial |
| Programmability | UV-erasable (windowed), field-programmable |
| Configuration Memory | Non-volatile EPROM (no external boot device) |
| Manufacturer | Altera Corporation (now Intel PSG) |
| Statut du cycle de vie | Obsolete (last produced by Altera, legacy stock via distributors) |
Configuration des broches de EPM5128GI
| Broche 1 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 2 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 3 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 4 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 5 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 6 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 7 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 8 | GND — Ground |
| Broche 9 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 10 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 11 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 12 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 13 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 14 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 15 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 16 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 17 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 18 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 19 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 20 | GND — Ground |
| Broche 21 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 22 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 23 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 24 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 25 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 26 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 27 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 28 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 29 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 30 | GND — Ground |
| Broche 31 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 32 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 33 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 34 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 35 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 36 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 37 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 38 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 39 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 40 | VCC — +5V supply |
| Broche 41 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 42 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 43 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 44 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 45 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 46 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 47 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 48 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 49 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 50 | GND — Ground |
| Broche 51 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 52 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 53 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 54 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 55 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 56 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 57 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 58 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 59 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 60 | VCC — +5V supply |
| Broche 61 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 62 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 63 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 64 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 65 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 66 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 67 | I/O — User I/O pin (bidirectional, programmable) |
| Broche 68 | I/O — User I/O pin (bidirectional, programmable) |
Applications typiques
EPM5128GI convient pour 6 applications: Industrial Control Glue Logic, Legacy 5V Bus Address Decoding, Prototype & Engineering Development Platform, Military & Aerospace Reprogrammable Logic, State-Machine Controllers, Legacy Peripheral Interfacing & Glue Logic.
Industrial Control Glue Logic
The EPM5128GI's 128 macrocells and deterministic 55 ns propagation delay make it a strong fit for industrial control glue logic that must run reliably without configuration boot time. Placed between a microcontroller and discrete I/O, it implements custom address decoding, watchdog handshakes, and interrupt prioritization; the ceramic CPGA-68 package provides hermetic sealing for factory-floor environments, while UV-erasability allows firmware revision during controller commissioning without board rework. The 5V supply matches legacy 5V industrial buses (e.g., STD-32, VME), and industrial temperature grade supports -40C to +85C operation typical of plant-floor enclosures.
Recommandé
Legacy 5V Bus Address Decoding
The EPM5128GI suits legacy 5V microprocessor bus address decoding where deterministic timing and non-volatile configuration are required. Its 55 ns tPD plus 128 macrocells can decode full 24-bit address spaces with multiple chip-select outputs and registered enables, fitting between a 5V CPU and peripherals like SRAM, ROM, or dual-ported memory. The ceramic CPGA-68 windowed package supports iterative firmware updates during prototype bring-up. Compared to 74LS/74FTTL decoder trees, the EPM5128GI consolidates logic, reduces board area, and offers one-chip revisionability via UV erasure for late-stage address-map changes.
Recommandé
Prototype & Engineering Development Platform
The EPM5128GI's UV-transparent ceramic window and 128-cell capacity make it ideal for prototype and pre-production development where logic must be iterated multiple times. Engineers using UV erasers can erase and reprogram the device 100+ times during logic development, with no in-circuit programming infrastructure needed beyond a standard Altera-compatible programmer. The CPGA-68 socketed package allows rapid swap of devices during test campaigns. Industrial temperature grade also lets prototypes move directly into field trials, accelerating time-to-validation for industrial and military designs that will eventually migrate to production OTP or surface-mount variants.
Recommandé
Military & Aerospace Reprogrammable Logic
The EPM5128GI's ceramic windowed CPGA-68 package, hermetic sealing, and UV-erasable non-volatile EPROM configuration suit military and aerospace applications where soldered SRAM FPGAs (which lose configuration on power-down) are unacceptable. With industrial temp grade as a baseline and the same Altera die used in military-screened variants, it provides a path for mission-critical avionics, weapons-system interfaces, and satellite command decoders requiring field reprogramming for software updates. The 5V supply rails match legacy MIL-STD-1553 and ARINC-429 interface hardware, and the deterministic 55 ns timing supports strict real-time control loops in flight systems.
Recommandé
State-Machine Controllers
The EPM5128GI's deterministic 55 ns timing and abundant macrocell registers make it well-suited for complex state-machine controllers in industrial automation, instrumentation, and embedded control applications. With 128 macrocells providing both combinatorial and registered logic, designers can implement multi-state FSMs, sequencers, and protocol engines without external glue logic. The UV-erasable ceramic package allows FSM revisions during algorithm development, while the non-volatile EPROM storage means the state machine boots instantly on power-up — critical for real-time control where SRAM-based FPGAs introduce unacceptable boot delays. Industrial temperature grade supports factory automation environments.
Recommandé
Legacy Peripheral Interfacing & Glue Logic
The EPM5128GI bridges legacy peripherals to modern microprocessors through custom interface glue logic, with 128 macrocells supporting parallel bus arbitration, wait-state generators, and protocol converters. Its 55 ns tPD handles ISA bus and similar 5V interfaces without timing violations, while the CPGA-68 ceramic package survives the thermal cycling of industrial enclosures. UV-erasability lets engineers tweak peripheral timing profiles during validation. The non-volatile configuration eliminates boot-PROM complexity compared to SRAM-based FPGAs, simplifying BOM and improving reliability in long-lifecycle industrial systems that must operate for decades without firmware-service infrastructure.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour EPM5128GI — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | EPM5128GC | EPM5128GC-1 | EPM5128GC-2 | EPM5128GC2 | EPM5128GI-1 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | CPGA-68 (ceramic windowed) | CPGA-68 - same | CPGA-68 - same | CPGA-68 - same | CPGA-68 - same | CPGA-68 - same |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 |
| Propagation Delay (tPD) | 55 ns | 55 ns | faster (-1 grade) | faster (-2 grade) | faster (-2 grade) | faster (-1 grade) |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Temperature Grade | Industrial | Commercial | Commercial | Commercial | Commercial | Industrial |
| Technology | UV-erasable CMOS EPROM | UV-erasable CMOS EPROM | UV-erasable CMOS EPROM | UV-erasable CMOS EPROM | UV-erasable CMOS EPROM | UV-erasable CMOS EPROM |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Principaux différenciateurs
- Industrial temperature grade (vs commercial-grade variants) (vs EPM5128GC)
- UV-erasable windowed ceramic package (vs EPM5128GM (military grade))
- Non-volatile EPROM configuration vs SRAM-based FPGAs (vs SRAM-based FPGAs (e.g., Xilinx XC4000 series))
Notes de conception
The EPM5128GI uses a CPGA-68 ceramic package that requires a PGA-68 socket — it is NOT surface-mountable. Attempting to hand-solder PGA leads will damage the ceramic body and break the UV-transparent window. Use a machined-pin socket (e.g., 3M Textool or equivalent) for development, and consider socketless PCB designs only for high-reliability production. Always verify the socket's pin numbering matches the Altera datasheet before insertion, as reverse-pin damage will destroy the device.
The EPM5128GI requires a single 5V ±10% supply with multiple VCC and GND pins distributed around the CPGA-68 package. Decouple each VCC pin with a 0.1 uF ceramic capacitor placed within 5 mm of the pin, plus a bulk 10-47 uF tantalum or aluminum capacitor at the board power entry. The device draws significant inrush current during UV erasure/programming — ensure your supply can deliver the current 200 mA peak with good regulation to prevent programming failures and EPROM read disturb.
Estimated: at 5V supply with all 128 macrocells switching at 18 MHz, the EPM5128GI dissipates approximately 1.5-2.0 W. The CPGA-68 ceramic package has a typical theta_JA of 30-40 C/W without airflow, giving a junction temperature rise of 45-80 C above ambient. For industrial environments with 60 C ambient, ensure adequate airflow or heat-sink attachment to the ceramic lid to keep Tj below 125 C. Always specify industrial-grade (GI) parts, not commercial (GC), for sustained operation above 70 C.
The EPM5128GI's 55 ns tPD is deterministic but I/O pin drive strength is limited (typically 4-8 mA source/sink). For buses with heavy capacitive loading (>50 pF), buffer outputs with external 74LS244/74FCT244 drivers rather than relying on direct CPLD drive. Add 10-33 ohm series damping resistors on high-speed outputs to reduce ground bounce on the CPGA-68 ceramic package, which can exhibit lead inductance around 10 nH per pin at fast edge rates.
Informations de conformité
RoHS and REACH status not documented in public Alldatasheet mirror as of 2026-09-12 (marked [DATA_NEEDED] in specs). Ceramic PGA package with through-hole leads predates RoHS enforcement; lead-free and halogen-free status marked unknown — verify with distributor environmental compliance documentation. AEC-Q100 not applicable — this is a programmable logic device, not an automotive-grade IC in the AEC-Q100 sense.
