EPM5128LC-1 vs EPM5130GI Comparaison
Comparaison détaillée côte à côte de EPM5128LC-1 par Altera et EPM5130GI par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5128LC-1 | EPM5130GI |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $8,20 | $16,20 |
| Family | MAX 5000 | — |
| Logic Elements / Macrocells | 128 macrocells | — |
| Number of Usable Gates | [DATA_NEEDED: usable gates] | — |
| Dedicated Inputs | 7 | 19 |
| Bidirectional I/O Pins | 52 | — |
| Total User I/O | 60 (max) | — |
| Propagation Delay (tpd) | 30 ns | — |
| Supply Voltage (VCC) | 5 V (±10%) | — |
| Process Technology | CMOS EPROM, UV-erasable | CMOS |
| Programmability | UV-erasable / OTP (windowed package) | — |
| Package Type | 68-pin J-lead ceramic chip carrier (PLCC windowed) | — |
| Température de fonctionnement | 0C to +70C (commercial) | -40C to +85C (industrial) |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| Type de montage | Surface Mount (J-lead PLCC socket compatible) | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device Family | — | MAX 5000 |
| Architecture | — | EPLD (Erasable Programmable Logic Device), UV-erasable |
| Macrocells | — | 128 |
| Logic Array Blocks (LABs) | — | 8 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Total Inputs | — | 68 |
| I/O Pins | — | 48 |
| Propagation Delay (tPD) | — | 55 ns |
| Maximum Clock Frequency (fMAX) | — | 33.3 MHz |
| External Clock Pins | — | 1 |
| Tension d'alimentation | — | 5 V |
| Boîtier | — | Ceramic Pin Grid Array (PGA), windowed |
| Programming Method | — | UV erasure + EPROM programming |