EPM5128LC-1 vs EPM5130GI 对比
详细并排对比 EPM5128LC-1 出自 Altera 和 EPM5130GI 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM5128LC-1 | EPM5130GI |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $8.20 | $16.20 |
| Family | MAX 5000 | — |
| Logic Elements / Macrocells | 128 macrocells | — |
| Number of Usable Gates | [DATA_NEEDED: usable gates] | — |
| Dedicated Inputs | 7 | 19 |
| Bidirectional I/O Pins | 52 | — |
| Total User I/O | 60 (max) | — |
| Propagation Delay (tpd) | 30 ns | — |
| Supply Voltage (VCC) | 5 V (±10%) | — |
| Process Technology | CMOS EPROM, UV-erasable | CMOS |
| Programmability | UV-erasable / OTP (windowed package) | — |
| Package Type | 68-pin J-lead ceramic chip carrier (PLCC windowed) | — |
| 工作温度 | 0C to +70C (commercial) | -40C to +85C (industrial) |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| 安装类型 | Surface Mount (J-lead PLCC socket compatible) | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device Family | — | MAX 5000 |
| Architecture | — | EPLD (Erasable Programmable Logic Device), UV-erasable |
| Macrocells | — | 128 |
| Logic Array Blocks (LABs) | — | 8 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Total Inputs | — | 68 |
| I/O Pins | — | 48 |
| Propagation Delay (tPD) | — | 55 ns |
| Maximum Clock Frequency (fMAX) | — | 33.3 MHz |
| External Clock Pins | — | 1 |
| 电源电压 | — | 5 V |
| 封装 | — | Ceramic Pin Grid Array (PGA), windowed |
| Programming Method | — | UV erasure + EPROM programming |