EPM51929C vs EPM5192AGC Comparaison
Comparaison détaillée côte à côte de EPM51929C par Intel et EPM5192AGC par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM51929C | EPM5192AGC |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,40 | $56,00 |
| Device Family | MAX 5000 | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | UV-Erasable / OTP Complex PLD (EPLD) |
| Architecture | Multi-array matrix (PAL-based macrocells) | CMOS, sum-of-products with macrocell output logic |
| Logic Density | [DATA_NEEDED: usable gates] | High-density (per MAX 5000 family definition) |
| Number of Macrocells | [DATA_NEEDED: macrocell count] | — |
| Nombre de broches | [DATA_NEEDED: pin count] | — |
| Package Type | [DATA_NEEDED: package suffix - C denotes commercial temperature grade] | — |
| Technology | CMOS EPROM | — |
| Programmability | UV-erasable, JEDEC fuse map | UV-erasable (windowed package) / One-Time-Programmable (windowless variant) |
| Température de fonctionnement | Commercial (0C to +70C) | [DATA_NEEDED: operating temperature range] |
| Tension d'alimentation | [DATA_NEEDED: VCC range] | [DATA_NEEDED: VCC nominal and tolerance] |
| Propagation Delay | [DATA_NEEDED: tpd specification] | — |
| Maximum Toggle Frequency | [DATA_NEEDED: fmax] | — |
| Type de montage | Surface Mount or Through-Hole (package dependent) | Through-hole (Pin Grid Array) |
| Statut RoHS | unknown | Non-compliant (ceramic PGA contains lead; legacy military/industrial grade) |
| Lead-Free | unknown | — |
| Niveau MSL | [DATA_NEEDED] | — |
| Family | — | MAX 5000 (High-Speed, High-Density MAX 5000 Devices) |
| Macrocells | — | 192 |
| Process Technology | — | CMOS |
| Boîtier | — | 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless) |
| Speed Grade Suffix | — | C (commercial grade; specific pin-to-pin delay varies by base number -15/-20) |
| Security Bit | — | Programmable security bit (per MAX 5000 family) |
| Lifecycle | — | Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs) |
| Programming Support | — | MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers |