EPM51929C vs EPM5192AGC Comparação
Comparação detalhada lado a lado de EPM51929C por Intel e EPM5192AGC por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EPM51929C | EPM5192AGC |
|---|---|---|
| Marca | Intel | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $9,40 | $56,00 |
| Device Family | MAX 5000 | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | UV-Erasable / OTP Complex PLD (EPLD) |
| Architecture | Multi-array matrix (PAL-based macrocells) | CMOS, sum-of-products with macrocell output logic |
| Logic Density | [DATA_NEEDED: usable gates] | High-density (per MAX 5000 family definition) |
| Number of Macrocells | [DATA_NEEDED: macrocell count] | — |
| Número de pinos | [DATA_NEEDED: pin count] | — |
| Package Type | [DATA_NEEDED: package suffix - C denotes commercial temperature grade] | — |
| Technology | CMOS EPROM | — |
| Programmability | UV-erasable, JEDEC fuse map | UV-erasable (windowed package) / One-Time-Programmable (windowless variant) |
| Temperatura de operação | Commercial (0C to +70C) | [DATA_NEEDED: operating temperature range] |
| Tensão de alimentação | [DATA_NEEDED: VCC range] | [DATA_NEEDED: VCC nominal and tolerance] |
| Propagation Delay | [DATA_NEEDED: tpd specification] | — |
| Maximum Toggle Frequency | [DATA_NEEDED: fmax] | — |
| Tipo de montagem | Surface Mount or Through-Hole (package dependent) | Through-hole (Pin Grid Array) |
| Status RoHS | unknown | Non-compliant (ceramic PGA contains lead; legacy military/industrial grade) |
| Lead-Free | unknown | — |
| Nível MSL | [DATA_NEEDED] | — |
| Family | — | MAX 5000 (High-Speed, High-Density MAX 5000 Devices) |
| Macrocells | — | 192 |
| Process Technology | — | CMOS |
| Encapsulamento | — | 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless) |
| Speed Grade Suffix | — | C (commercial grade; specific pin-to-pin delay varies by base number -15/-20) |
| Security Bit | — | Programmable security bit (per MAX 5000 family) |
| Lifecycle | — | Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs) |
| Programming Support | — | MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers |