EPM51929C vs EPM5192AGC-15 Comparaison
Comparaison détaillée côte à côte de EPM51929C par Intel et EPM5192AGC-15 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM51929C | EPM5192AGC-15 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,40 | $27,80 |
| Device Family | MAX 5000 | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Architecture | Multi-array matrix (PAL-based macrocells) | — |
| Logic Density | [DATA_NEEDED: usable gates] | — |
| Number of Macrocells | [DATA_NEEDED: macrocell count] | — |
| Nombre de broches | [DATA_NEEDED: pin count] | — |
| Package Type | [DATA_NEEDED: package suffix - C denotes commercial temperature grade] | — |
| Technology | CMOS EPROM | CMOS, UV-erasable EPROM |
| Programmability | UV-erasable, JEDEC fuse map | — |
| Température de fonctionnement | Commercial (0C to +70C) | [DATA_NEEDED: operating temperature range] |
| Tension d'alimentation | [DATA_NEEDED: VCC range] | — |
| Propagation Delay | [DATA_NEEDED: tpd specification] | — |
| Maximum Toggle Frequency | [DATA_NEEDED: fmax] | — |
| Type de montage | Surface Mount or Through-Hole (package dependent) | — |
| Statut RoHS | unknown | [DATA_NEEDED: RoHS status - legacy ceramic PGA typically non-compliant] |
| Lead-Free | unknown | — |
| Niveau MSL | [DATA_NEEDED] | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Series | — | MAX 5000 |
| Macrocells | — | 192 |
| Logic Array Blocks | — | 16 (typical for 192-macrocell MAX 5000) |
| Maximum User I/O Pins | — | 64 |
| Dedicated Inputs | — | 7 |
| Total Inputs | — | 72 |
| Propagation Delay (tPD) | — | 15 ns (pin-to-pin, -15 speed grade) |
| Supply Voltage (VCC) | — | 5 V |
| Boîtier | — | Ceramic Pin Grid Array (PGA) |
| Programming Method | — | UV erase + EPROM program (via Altera programmer) |
| Statut du cycle de vie | — | Obsolete / Last Time Buy (per Altera legacy product list) |